JPS6335152U - - Google Patents

Info

Publication number
JPS6335152U
JPS6335152U JP12154487U JP12154487U JPS6335152U JP S6335152 U JPS6335152 U JP S6335152U JP 12154487 U JP12154487 U JP 12154487U JP 12154487 U JP12154487 U JP 12154487U JP S6335152 U JPS6335152 U JP S6335152U
Authority
JP
Japan
Prior art keywords
bus
signal
selectively
digital information
bidirectionally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12154487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS6335152U publication Critical patent/JPS6335152U/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１ａ図乃至第１ｄ図はメモリから読出すため
に用いられる場合の本考案の動作を示した概要図
、第２ａ図乃至第２ｄ図はメモリに書込むために
用いられる場合の本考案の動作を示した概要図、
第３図は符号化チツプ選択信号を供給するための
装置の概要図である。 ２０ａ，２０ｂ……メモリ、２２ａ，２２ｂ…
…データバス、２４ａ，２４ｂ，２８，３０……
トランシーバ、２６ａ，２６ｂ……システムバス
、３２……バツフア、３４，３８，４４，４６…
…インバータ、３６，４０，４２……ＮＡＮＤゲ
ート。 Figures 1a to 1d are schematic diagrams illustrating the operation of the present invention when used to read from memory, and Figures 2a to 2d are schematic diagrams illustrating the operation of the present invention when used to write to memory. A schematic diagram showing
FIG. 3 is a schematic diagram of an apparatus for providing a coding chip selection signal. 20a, 20b...memory, 22a, 22b...
...Data bus, 24a, 24b, 28, 30...
Transceiver, 26a, 26b... System bus, 32... Bus, 34, 38, 44, 46...
...Inverter, 36, 40, 42...NAND gate.

Claims (1)

【実用新案登録請求の範囲】 (1) 少くとも第１及び第２のバス間においてデ
イジタル情報を双方向性をもつて選択的に転送す
る回路であつて、 第１バスの第１部分及び第２バスの第１部分の
間でデイジタル情報の第１部分を双方向性をもつ
て選択的に転送するための第１手段にして、前記
第１および第２のバスに結合されている第１手段
と、 前記第１バスの第２部分及び第２バスの第２部
分の間で前記デイジタル情報の第２部分を双方向
性をもつて選択的に転送するための第２手段にし
て、前記第１バスの第２部分および前記第２バス
の第２部分に結合されている第２手段と、 前記第２バスの前記第１部分と前記第１バスの
前記第２部分間で前記デイジタル情報の前記第２
部分を双方向性をもつて選択的に転送するための
スワツプ手段にして、前記第１バスの前記第２部
分と前記第２バスの前記第１部分との間に結合さ
れているスワツプ手段とを備え、 前記第１手段と前記第２手段および前記スワツ
プ手段は、第１信号とエネーブル用第２信号とに
より、選択的にエネーブルにさせられ、 もつて、バイト長と語長の両方のデイジタル情
報を同時処理できるコンピユータ構成を可能とす
るように、デイジタル情報のバイトと語とを双方
向性をもつて選択的に転送できることを特徴とす
る、デイジタル情報を双方向性をもつて選択的に
転送する回路。 (2) 実用新案登録請求の範囲第１項記載の回路
において、デイジタル情報の第１及び第２部分は
各々８ビツトから成ることを特徴とする回路。 (3) 実用新案登録請求の範囲第１項記載の回路
において、第１信号は第２バス上のアドレス信号
の最下位信号であることを特徴とする回路。 (4) 実用新案登録請求の範囲第１項記載の回路
において、スワツプ手段は第１バスの第２部分と
第２バスの第１部分間に直接結合されることを特
徴とする回路。 (5) 実用新案登録請求の範囲第１項記載の回路
において、第１信号はアドレスバス上の最下位ビ
ツトＡＤＲＯを含み、第２信号はデイスクリート
コマンド信号ＢＨＥＮを含むことを特徴とする回
路。[Claims for Utility Model Registration] (1) A circuit that selectively transfers digital information bidirectionally between at least a first and a second bus, which a first means for bidirectionally selectively transferring a first portion of digital information between first portions of two buses, the first means being coupled to the first and second buses; means for bi-directionally selectively transferring a second portion of the digital information between a second portion of the first bus and a second portion of the second bus; second means coupled to a second portion of the first bus and the second portion of the second bus; Said second
swap means for bi-directionally selectively transferring portions, the swap means being coupled between the second portion of the first bus and the first portion of the second bus; the first means, the second means and the swapping means are selectively enabled by a first signal and a second enabling signal, and wherein the first means, the second means and the swapping means are selectively enabled by a first signal and a second enabling signal; A system for bidirectionally and selectively transmitting digital information, characterized by the ability to bidirectionally and selectively transfer bytes and words of digital information, so as to enable computer configurations that can process information simultaneously. circuit to transfer. (2) The circuit according to claim 1, wherein the first and second parts of the digital information each consist of 8 bits. (3) Utility Model Registration The circuit according to claim 1, wherein the first signal is the lowest signal of the address signals on the second bus. (4) The circuit according to claim 1, characterized in that the swap means is directly coupled between the second portion of the first bus and the first portion of the second bus. (5) Utility Model Registration The circuit according to claim 1, wherein the first signal includes the least significant bit ADRO on the address bus, and the second signal includes the discrete command signal BHEN.
JP12154487U 1978-05-30 1987-08-10 Pending JPS6335152U (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US91010378A 1978-05-30 1978-05-30

Publications (1)

Publication Number Publication Date
JPS6335152U true JPS6335152U (en) 1988-03-07

Family

ID=25428316

Family Applications (2)

Application Number Title Priority Date Filing Date
JP6456379A Pending JPS54157048A (en) 1978-05-30 1979-05-23 Circuit for and method of transferring digital information
JP12154487U Pending JPS6335152U (en) 1978-05-30 1987-08-10

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP6456379A Pending JPS54157048A (en) 1978-05-30 1979-05-23 Circuit for and method of transferring digital information

Country Status (7)

Country Link
JP (2) JPS54157048A (en)
CA (1) CA1129110A (en)
DE (1) DE2921419A1 (en)
FR (1) FR2427648A1 (en)
GB (1) GB2021823B (en)
HK (1) HK14285A (en)
SG (1) SG61084G (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0558814U (en) * 1992-01-13 1993-08-03 日産ディーゼル工業株式会社 Particulate trap filter regeneration device

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1121031B (en) * 1979-09-19 1986-03-26 Olivetti & Co Spa MULTIPROCESSOR DATA PROCESSING SYSTEM
JPS56132624A (en) * 1980-03-19 1981-10-17 Toshiba Corp Information processor
US4371928A (en) * 1980-04-15 1983-02-01 Honeywell Information Systems Inc. Interface for controlling information transfers between main data processing systems units and a central subsystem
JPS5779551A (en) * 1980-11-06 1982-05-18 Nec Corp Information transfer device
JPS57121746A (en) * 1981-01-22 1982-07-29 Nec Corp Information processing device
US4500958A (en) * 1982-04-21 1985-02-19 Digital Equipment Corporation Memory controller with data rotation arrangement
DE3241356A1 (en) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München DEVICE FOR MICROPROGRAM CONTROL OF AN INFORMATION TRANSFER AND METHOD FOR THEIR OPERATION
JPS59226923A (en) * 1983-05-27 1984-12-20 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン Bus interface apparatus
FR2548489B1 (en) * 1983-06-30 1986-12-05 Num Sa COUNTING CIRCUIT IN PARTICULAR FOR ASSOCIATED WITH AN INCREMENTAL SENSOR AND CAPABLE OF COOPERATING WITH AN EIGHT OR SIXTEEN BINARY COMPUTER
DE3400673A1 (en) * 1984-01-11 1985-07-18 Robert Bosch Gmbh, 7000 Stuttgart Microcomputer
JPS60160425A (en) * 1984-02-01 1985-08-22 Hitachi Ltd Connecting circuit
US4621341A (en) * 1984-08-24 1986-11-04 Advanced Micro Devices, Inc. Method and apparatus for transferring data in parallel from a smaller to a larger register
US4716527A (en) * 1984-12-10 1987-12-29 Ing. C. Olivetti Bus converter
JPS61139866A (en) * 1984-12-11 1986-06-27 Toshiba Corp Microprocessor
JPS61175845A (en) * 1985-01-31 1986-08-07 Toshiba Corp Microprocessor system
BG45007A1 (en) * 1987-03-19 1989-03-15 Khristo A Turlakov
GB2211326B (en) * 1987-10-16 1991-12-11 Hitachi Ltd Address bus control apparatus
JPH01300361A (en) * 1988-05-28 1989-12-04 Nec Eng Ltd Microprocessor system
GB2222471B (en) * 1988-08-29 1992-12-09 Mitsubishi Electric Corp Ic card with switchable bus structure
JP2539012B2 (en) * 1988-09-28 1996-10-02 富士通株式会社 Memory card
DE3900348A1 (en) * 1989-01-07 1990-07-12 Diehl Gmbh & Co UNIVERSAL BUS SYSTEM
JPH0648774Y2 (en) * 1989-09-21 1994-12-12 沖電気工業株式会社 Card type integrated circuit and connector terminal structure
US5115411A (en) * 1990-06-06 1992-05-19 Ncr Corporation Dual port memory system
JP3226055B2 (en) * 1992-09-16 2001-11-05 松下電器産業株式会社 Information processing device
KR19980033054A (en) 1996-10-23 1998-07-25 윌리엄비.켐플러 Programmable Memory Access

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5195740A (en) * 1975-02-20 1976-08-21 Chokusetsumemori akusesuseigyohoshiki

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1254929A (en) * 1969-03-26 1971-11-24 Standard Telephones Cables Ltd Improvements in or relating to digital computers
CA1120123A (en) * 1976-11-11 1982-03-16 Richard P. Kelly Automatic data steering and data formatting mechanism

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5195740A (en) * 1975-02-20 1976-08-21 Chokusetsumemori akusesuseigyohoshiki

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0558814U (en) * 1992-01-13 1993-08-03 日産ディーゼル工業株式会社 Particulate trap filter regeneration device

Also Published As

Publication number Publication date
JPS54157048A (en) 1979-12-11
GB2021823B (en) 1983-04-27
DE2921419C2 (en) 1990-12-20
FR2427648B1 (en) 1985-03-01
CA1129110A (en) 1982-08-03
GB2021823A (en) 1979-12-05
DE2921419A1 (en) 1979-12-13
HK14285A (en) 1985-03-08
SG61084G (en) 1985-03-15
FR2427648A1 (en) 1979-12-28

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