JPS6415856A - Direct memory access system - Google Patents

Direct memory access system

Info

Publication number
JPS6415856A
JPS6415856A JP17219187A JP17219187A JPS6415856A JP S6415856 A JPS6415856 A JP S6415856A JP 17219187 A JP17219187 A JP 17219187A JP 17219187 A JP17219187 A JP 17219187A JP S6415856 A JPS6415856 A JP S6415856A
Authority
JP
Japan
Prior art keywords
address
memory
order
input
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17219187A
Other languages
Japanese (ja)
Inventor
Shinichi Kosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17219187A priority Critical patent/JPS6415856A/en
Publication of JPS6415856A publication Critical patent/JPS6415856A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

PURPOSE:To avoid a sharing state of a memory space for transfer of data by sharing a low-order address bit which designates a memory address between a main device and an input/output device and at the same time producing a high-order address bit via a control circuit of an input/output circuit. CONSTITUTION:A control circuit 21 of an input/output device 2 transmits the signals A0-A7 of low-order N bits which designate the addresses of a main memory 11 and an input/output memory 25 as well as a read/write signal R/W via an address line 41 and a R/D control line 42 which are connected in common to a DMA controller 22. At the same time, the signals A8-A15 of high-order P bits which designate the address of the memory 11 are sent to an address line 43 via an address latch circuit 23. Furthermore the signals A8-A15 of high-order Q bits which designate the address of the memory 25 are sent to an address line 44 via an address latch circuit 24 respectively. Both memories 11 and 25 are connected to each other via a common data transfer line 45 so that common memory space is not needed for transfer of data between both memories 11 and 25.
JP17219187A 1987-07-10 1987-07-10 Direct memory access system Pending JPS6415856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17219187A JPS6415856A (en) 1987-07-10 1987-07-10 Direct memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17219187A JPS6415856A (en) 1987-07-10 1987-07-10 Direct memory access system

Publications (1)

Publication Number Publication Date
JPS6415856A true JPS6415856A (en) 1989-01-19

Family

ID=15937263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17219187A Pending JPS6415856A (en) 1987-07-10 1987-07-10 Direct memory access system

Country Status (1)

Country Link
JP (1) JPS6415856A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008234112A (en) * 2007-03-19 2008-10-02 Fujitsu Ltd Data transmission control method and device in cpu control bus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008234112A (en) * 2007-03-19 2008-10-02 Fujitsu Ltd Data transmission control method and device in cpu control bus

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