JPS585133U - data transmission system - Google Patents

data transmission system

Info

Publication number
JPS585133U
JPS585133U JP9811081U JP9811081U JPS585133U JP S585133 U JPS585133 U JP S585133U JP 9811081 U JP9811081 U JP 9811081U JP 9811081 U JP9811081 U JP 9811081U JP S585133 U JPS585133 U JP S585133U
Authority
JP
Japan
Prior art keywords
data transmission
processor
transmission system
slave processor
pui
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9811081U
Other languages
Japanese (ja)
Inventor
勝木　格
Original Assignee
株式会社島津製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社島津製作所 filed Critical 株式会社島津製作所
Priority to JP9811081U priority Critical patent/JPS585133U/en
Publication of JPS585133U publication Critical patent/JPS585133U/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

Claims (1)

【実用新案登録請求の範囲】 １　主局プロセッサＰＵＱと従局プロセッサＰＵ１間に
それぞれのアドレス・データ共用バスＢＳと制御信号Ｃ
３−ＭＷ−ＭＲとでもって接続された一時記憶回路１０
が配置され、一時記憶回路１０は、複数レジスタからな
り、データ伝送元プロセッサに対しては書込み用に、デ
ータ伝送。 先プロセッサに対しては読出し用に使用される一時メモ
リＭと該レジスタのセレクタＳとを有し、特定レジスタ
Ａをフラグとして利用することを特徴とする、データ伝
送システム。 ２　メモリ書込み信号ＭＷを介して、５ＴＡＲＴ信号に
接続されたゲートＧを従局プロセッサＰＵｌのバスＳＢ
ｌに介在させることにより、従局プロセッサＰＵＩの一
時メモリＭに対するアクセスを制御することを特徴とす
る、データ伝単システム。[Claims for Utility Model Registration] 1 Address/data shared bus BS and control signal C between the master processor PUQ and the slave processor PU1.
Temporary storage circuit 10 connected with 3-MW-MR
The temporary storage circuit 10 consists of a plurality of registers, and is used for data transmission to the data transmission source processor for writing. A data transmission system comprising a temporary memory M used for reading to a previous processor and a selector S for the register, and using a specific register A as a flag. 2 The gate G connected to the 5TART signal is connected to the bus SB of the slave processor PUl via the memory write signal MW.
1. A data transmission system, characterized in that access to a temporary memory M by a slave processor PUI is controlled by intervening in a slave processor PUI.
JP9811081U 1981-06-30 1981-06-30 data transmission system Pending JPS585133U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9811081U JPS585133U (en) 1981-06-30 1981-06-30 data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9811081U JPS585133U (en) 1981-06-30 1981-06-30 data transmission system

Publications (1)

Publication Number Publication Date
JPS585133U true JPS585133U (en) 1983-01-13

Family

ID=29892878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9811081U Pending JPS585133U (en) 1981-06-30 1981-06-30 data transmission system

Country Status (1)

Country Link
JP (1) JPS585133U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60139038U (en) * 1984-02-24 1985-09-13 石川島播磨重工業株式会社 Turbocharger bearing compartment
JPS61262876A (en) * 1985-05-15 1986-11-20 Nec Corp Multiprocessor system
JPS6447938U (en) * 1987-09-18 1989-03-24

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60139038U (en) * 1984-02-24 1985-09-13 石川島播磨重工業株式会社 Turbocharger bearing compartment
JPS61262876A (en) * 1985-05-15 1986-11-20 Nec Corp Multiprocessor system
JPS6447938U (en) * 1987-09-18 1989-03-24
JPH0536995Y2 (en) * 1987-09-18 1993-09-20

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