CA1129110A

CA1129110A - Apparatus and method for providing byte and word compatible information transfers

Info

Publication number: CA1129110A
Application number: CA327,297A
Authority: CA
Inventors: D. Craig Kinnie; Richard W. Boberg
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 1978-05-30
Filing date: 1979-05-09
Publication date: 1982-08-03
Also published as: GB2021823A; DE2921419C2; DE2921419A1; FR2427648A1; HK14285A; JPS54157048A; FR2427648B1; JPS6335152U; SG61084G; GB2021823B

Abstract

ABSTRACT OF THE DISCLOSURE

A digital processor, memory or other digital in-formation circuit can be made compatible in a computer system which includes both 8 or 16 bit digital users within the system.
The 16 bit system and local buses are divided into an upper and lower half with each half having a separate upper and lower buffer circuit respectively. A swap byte buffer is provided for selectively coupling digital information on the upper half of the local bus to the lower half of the system bus. The lower, upper, and swap byte buffers are selectively enabled in response to a discrete command signal and in the case of memory transfers, to the least significant bit of the memory address.

Description

1. Field of the Invention The present invention relates to apparatus and methods for transferring information between a local and system bus wherein the users and peripherals connected with these busses are each characterized by differing lengths of the units of digital information processed. In particular, the present invention relates to a method and apparatus which in combination with well-known control circuitry permits the use of both 8 and 16 bit machines in the same system.

2. Description of the Prior Art Semiconductor microprocessors have predominantly been designed to transfer data or digital information within a microprocessor computer system, for example, as between a processor and a memory, wherein the information consisted of eight-bit bytes. Thus, a large number of peripheral devices are organized and accessed in byte quantities.

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: ' 1 However, the sophistication, power and complexity of semiconductor microprocessors continues to increase at an accelerating rate wherein many microprocessor computer systems are now based upon manipulation of quantities having a word or 16 bit lenyths. Thus, many prior art eight-bit memories can no longer be accessed by central processors which assume that each memory location contains a sixteen-bit word. Therefore, a sub-stantial number of prior art microprocessor computer systems, including peripherals, have become incompatible with newer sixteen-bit microprocessor systems now being developed and marketed. What is needed then is some means by which a computer system may be organized so as to be compatible with circuit users and peripherals based both upon byte and word legth quantities.
BRIEF SUMMAR~ OF THE INVENTION
The present invention is a circuit for transferring digital information~ having units of length of at least two magnitudes, between a first and second bus. The circuit com-prises a first means for selectively transferring a first portion of the digital information between a first portion of the first bus and a first portion of the second bus. A second means is provided for selectively transferring a second portion of the digital information between a second portion of the first bus and a second portion of the second bus. A swap means is then providefl for selectively transferring the second portion of the digital information between he second portion of the first bus and the first portion of the second bus. By this means a circuit can be devised for selectively transferring bytes and words of diyital information to provide 1 a computer organization compatible with the concurrent processing 2 of both byte and word length digital information.

3 More specifically, the present invention is a circuit

4 for selectively transferring byte and words of digital informa-tion between the local and system bus wherein the local and 6 system bus each have a lower and upper portion. The circuit 7 comprises a lower transceiver circuit or buffer for transferring 8 the digital information between the lower portions of the local 9 and system busses. An upper transceiver circuit or buffer is provided for transferring the digital information b`etween the 11 upper portions of the local and system busses. Finally, a swap 12 byte transceiver circuit or buffer is included for transferring 13 the digital information between the lower portion of a system 14 bus and the upper portion of a local bus. In one embodiment the swap byte transceiver circuit or buffer is coupled directly 16 between the upper portion of the local bus and the lower portion 17 of the system bus. In another embodiment the swap byte trans-18 ceivers circuit or buffer is coupled between the upper and lower 19 portion of local bus to communicate with the lower portion of the system bus through the lower transceiver circuit or buffer.
21 The present invention also includes a method for 22 transferring information between a local and system bus wherein 23 the local and system bus each have a lower and upper portion.
24 The method comprises the step of decoding a discrete command signal and a least significant address bit to selectively 26 generate a plurality of chip select signals. At least one 27 of the plurality of chip select signals is indicative of a 28 transfer of information between the lower portion of the 29 system bus and the upper portion of a local bus. Next, a 33l 3.

Z9110 1 `

1 plurality of transceiver circuits are selectively enabled to 2 selectively transfer the information between the upper and lower ~ portions of the local and system bus. At least one of the 4 plurality of transceiver circuits is selectively enabled to transfer the information between the lower portion of the system 6 bus and the upper portion of the local bus. These and the other 7 advantages and embodiments of the present invention are best 8 understood by viewing the drawings in light of the following 9 Detailed Description of the Preferred Embodiments.

11 BRIEF DESCRIPTIO~ OF THE DRAWINGS
12 FIGURES la through ld are diagrammatic ill~strations 13 of the operation of the present invention when used to read 14 from a memory;
FIGURES 2a through 2d are diagrammatic ill~strations 16 using the present invention to write into a memory; and 17 FIGURE 3 shows in simplified form one means for pro-18 viding the coded chip select signalsO

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
21 The present invention is circuitry and a method for 22 organizing digital circuitry such that the digital circuit, 23 processor, memory or like device may access a system bus to 24 transfer either byte or word length quantities of digital information onto and from the system bus. The 16 bit system 26 bus is divided into two halves each consisting of 8 bit bytes.
27 D~ta transceivers are provided for both the upper and lower 2b ves of the system bus. A swap byte transceiver is similarly 4.

1 provided to couple the upper portion of the local bus to the 2 lower portion of the system bus. Both the upper and lower 3 transceivers and the swap byte transceiver are selectively 4 enabled in response to two encoded signals: a byte high enable, BHEN, which is a discrete processor command signal, and ADRO, 6 which may generally be regarded as the least significant bit q of the system address bus. Thus, by appropriately enabling 8 the transceivers, a full 16 bit word may be transferred or a 9 single 8 bit word transferred on either the upper or lower halves of the system bus to the upper or lower halves of the 11 local bus or may be switched between the upper half of the 12 local bus and the lower half of the system bus.
13 The embodiment which is illustrated is assumed to 14 be a memory card having a memory bank divided into low or even lS address bytes and high or odd address bytes. Thus, when the 16 term "local bus" is used it is intended to mean the data bus 17 which is incorporated on the memory card and upon which digital 18 information is transferred between the memory and the memory 19 card transceivers. Similarly, the term "system bus" is taken to mean the object bus to which the transceivers convey or 21 receive digital information. It is entirely within the scope 22 of the present invention that what is termed herein as the 23 system bus may not have a plurality of peripherals or users 24 attached thereto and may instead have a single processor which accesses a single memory bank through transceivers organized 26 according to the present invention. On the other hand, it is 2d ~ turtbe be understood thst what is termed herein as a local ~2 11 ~9110 1 bus need not communicate with a memory bank but may communicate 2 with a processor of any type known to the art, such as a central 3 processor, a dedicated processor, an input/output processor, 4 and subprocessing circuitry such as a direct memory access controller. Thus, the data transceivers of the present invention ~ as illustrated in the FIGURES may in fact permit a processor 7 to communicate with a true system bus in which case the local 8 bus is a processor local bus. The particular embodiment which 9 is illustrated is not taken to limit or restrict the scope of the present invention but is only provided for the purpose of clari-11 fying the nature of the present invention by presenting a single 12 illustrated embodiment.
13 The circuitry and methodology of the present invention 14 may be better understood by referring to FIGURES la through ld lS which symbolically represent a memory/read operation. In EIGURE
16 la memory bank 20 is comprised of a low or even bank 20a for 17 storage of bytes having an even address and a high or odd bank 18 20b for storage of bytes having an odd address. An 8 bit data 19 line 22a provides a bidirectional bus for memory 20a. Similarly, 8 bit bidirectional data bus 22b provides the same function for 21 memory 20b. Together, busses 22a and 22b form a 16 bit data 22 bus characterized by having a lower or first portion 22a and 23 an upper or second portion 22b. Again, although the presently 24 illustrated embodiment shows a local bus as being a data bus, it must be expressly understood that digital information, other 26 than data, may be transferred over the busses of the present 27 i en t ion .

~2 l Data bus 22a is coupled to transceiver or buffer 24a.
2 Similarly, bus 22b is coupled to transceiver or buffer 24b.
3 Transceiver 24a is also coupled to the first or lower portion of 4 a system bus 26a, DAT0-DAT7. Similarly, transceiver 24b is

5 coupled to the upper or second portion of system bus 26b, DAT8-

6 DATF. FIGURES la through ld, and 2a through 2d each illustrate

7 two possible embodiments of the present invention. In one

8 embodiment a byte swap transceiver 28 is coupled directly between

9 busses 22a and 22b. In this embodiment bytes are transferred between memory bank 20b and system bus 26a through transceiver 11 28 and transceiver 24a. In another embodiment, a transceiver 30 12 is directly coupled between bus 22b and 26a thereby providing 13 direct communication between the high memory bytes and the lower 14 portion of the system bus. Each of the FIGURES lb through ld and 2a through 2d are similarly configured and numbered.
16 In an 8 bit system only the lower eight lines 26a of 17 the system bus will be used for transferring digital informa-18 tion. Therefore, both even and odd bytes are accessed through l9 lower portion 26a of the system bus. In the case where even bytes are accessed, encoded signals BHEN and ADR0 are both 21 true, transceiver 24a is enabled by means described below and the 22 information is transferred from bus 22a to 26a. In the case 23 where an odd address is accessed, the encoded signal ~HEN is 24 true and ADR0 is false as illustrated in FIGURE lb. In one embodiment transceiver 30 is enabled thereby allowing trans-26 fer of the odd byte digital information directly from bus 22b to 27 26a. In another embodiment transceivers 2~ and 24a are both 28 enabled to transfer the odd byte information from bus 22b to 29 bus 22a and then to bus 26a.

3l 7.

1~ In a 16 bit system, a 16 bit word may be simultaneously 21 accessed from the even and odd addresses by providing the encoded 31 signals BHEN false and ADR0 true to enable both transceivers 41 24a and 24b. The even address byte is transferred on bus 22a to 51 26a while the odd address byte is transferred on bus 22b to 26b 6 las illustrated in FIGURE lc.
71 It is also possible in a 16 bit system to address 16 8 ¦bit words which begin on odd addresses by using two transfer 9 ¦cycles. The odd address byte is acces-sed as illustrated in

10 ¦FIGURE ld by the encoded signals BHEN and ADR0 both false

11 ¦thereby transferring the information on busses 22b and 26b.

12 ¦The even address byte may then be accessed by providing the

13 ¦encoded signals to enable transceiver 24a as illustrated in

14 ¦FIGURE la.

15 ¦ A memory write operation proceeds in the identical

16 ¦manner with the same coding as can be appreciated by viewing

17 ¦FIGURES 2a through 2d. The transfer of digital information

18 ¦between the upper and lower halves of the local and system

19 ¦busses is identical with respect to both write and read opera-

20 ¦tions with the exception that the direction of data flow is

21 ¦reversed. Reversal is achieved by coupling an appropriate data

22 ¦transmit or receive signal, DT/R, to each of the transceivers

23 as illustrated and discussed below. The memory write operations

24 are distinguished from the memory read operations by selectively

25 generating a conventional memory read or memory write command

26 signal from the processor or other controlling circuitry.

27 One means by which the plurality of transceivers of

28 the present invention may be selectively enabled is illustrated

29 in detail in FIGURE 3. The system signals, byte high enable, 3l 32 a.

il l BHEN and the least significant bit of the address bus ADR0 are 2 buffered through a conventional inverting buffer 32 which serves 3 to isolate and buffer the system signals from the internal 4 circuitry of the memory card. The output, BHEN, of conventional buffer 32 is then inverted by inverter 34 whose output in turn 6 is coupled to one input of AND gate 36. The other output of 7 buffer 32, ADR0, is coupled directly to the other input of MAND
8 gate 36. The output of NAND gate 36 is the signal SWAP BYTE.
9 As can be confirmed by comparison with FIGURES lb and 2b SWAP
BYTE is active low whenever ADRO is false and BHEN is true.
ll SWAP BYTE is then inverted by inverter 38 and coupled to one 12 input of NAND gate 40. The other input of NAND gate 40 is 13 coupled to the local control signal BUS DISABLE. B~S DISABLE
14 lS an internal signal generated by the memory card in a conven-tional means to appropriately enable and disable transceivers 16 24a, 24b and 28 or 30 consistent with the timing and control 17 to which memory 20 is subjected. BUS DISABLE and SWAP BYTE
18 are each coupled to the inputs of NAND gate 42. The output l9 of NAND gate 42 is coupled to the chip select input, CS, of transceivers 24a and 24b. The output of NAND gate 40 is the 21 signal, SWAP EN which is coupled to the CS input of transceiver 22 30.
23 E'IGURE 3 is specifically directed to that embodiment 24 illustrated in FIGURES la through ld, and 2a through 2d in which the transceiver is coupled directly between bus 22b and 26 26a. The truth table for both embodiments is listed below 27 in TABLE l.

9' LINES TRANSCEIVER CONTROL CHIP SELECT
.~ ._ . _ _, _ 3 _ _ ___ LOWER X'TR SWAP UPPER X'TR LOWER UPPER
4 B EN ALRO -ENABLE ENLB EN ENSB ENABLE E~U~ CSLB CSUB

6 1~ ~ ~ 1(0)~ o ~ o 9 X = Don't Care ENLB = 1 or (ENLB = ENSB)*
11 ENSB = BHEN . ADR0 12 ENUB = ENSB or BHEN
13 CSLB = ADR0 14 CSUB = BHEN + ADRO
5¦ * Alternate SWAP transceiver 30 configuration.
161 .

7¦ Appropriate logic circuitry for implementing that embodiment 8¦ wherein transceiver 28 is employed can easily be devised 9¦ according to the teachings of the present invention.
20¦ The internal circuitry of transceiver 24a in simplified 21¦ form is diagrammatically illustrated in FIGURE 3. Each of the 22¦ bidirectional bus lines is coupled to a pair of conventional 231 tristate inverters 44 and 46. Consider, for example, the line 2~ ¦ DAT0. Information presented at terminal 48 is coupled to tri-25 ¦ state inverter 44, inverted and communicated to terminal 50.
26 ¦ Similarly, information being transferred into the memory card 27 ¦ is coupled through tristate inverter 46 from terminal 50, which 28 ¦ is now an input, to terminal 48, as an output. Output inverter 23391 44 is tristated by AND gate 52 while input inverter 46 is 32 ~
.' . ' 10.

1~ 1329110 1 tristated by AND gate 54. The local bus control signal DT/R is 2 coupled to the transmit or T inputs of each of the transceivers 3 24a, 24b, 28 or 30. Thus, when CS is active low, the output inverters will be enabled when the T input is low and the input inverters enable when the T input is high. Otherwise, each 6 of the bus lines in lower portion 26a will be tristated or 7 set in an high impedance state.
8 Each of the transceivers 24a, 24b, 28 or 30 are identically configured. Therefore, the don't care states as ~0 listed in TABLE 1 above, allow transceivers 24a and 24b to be 11 enabled and disenabled in an identical fashion in the embodiment 12 which utilizes transceiver 30 as illustrated in FIGURE 3. The 13 output of NAN~ gate 40, SWAP EN only goes active low to enable 14 transceiver 30 when B~EN is true and ADR0 is false as indicated in TABLE 1. Similarly, by conventional decoding BHEN and ADR0 16 can be provided as chip select signals for the lower and upper 17 halves 20a and 20b respectively of memory 20 in the manner 18 also illustrated in TABLE 1.
9 Thus, by coupling a memory 20 to a system bus having lower and upper portions 26a and 26b respectively, as illustrated 21 in FIGURE 3 the memory may be accessed either as 8 bit or 16 bit 22 memory accordlng to two encoded signals such that the memory may 23 be totally compatible in a computer system having both 8 and 16 24 bit processors or peripherals. By using the least significant bit of the address bus as the lower byte enable, and providing 26 a separate byte high enable signal, the encoding system of the 27 present invention may also be made compatible, as illustrated 28 herein, with the conventional 8 bit system wherein ADR0 is 239 typically used as an enabling signal.

11.

ll~9~La 1 It must be understood that many modlfications and 2 alterations may be made to the illustrated embodiment while 3 still remaining within the spirit and scope of the present 4 invention. For example, although the discussion has been in terms of an 8 and 16 bit duality, the invention may be employed 6 with equal ease in systems having other dualities such as 16-bit 7 and 32-bit systems. Further, although the present invention 8 has generally been discussed as involving the transfer of digital 9 information between a memory or peripheral and processor, the methodology and apparatus of the present invention to be egually 11 advantageous in any situation involving the transfer of digital 12 information betweén two or more busses having distinguishable portio es 32 12.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A circuit for bidirectionally and selectively trans-ferring digital information between at least a first and second bus comprising:
a first means for bidirectionally, and selectively transferring a first portion of said digital information between a first portion of said first and second busses, said first means coupled to said first portion of said first and second busses;
second means for bidirectionally and selectively trans-ferring a second portion of said digital information between a second portion of said first and second busses, said second means coupled to said second portion of said first and second busses;
and swap means for bidirectionally and selectively trans-ferring said second portion of said digital information between said first portion of said second bus and said second portion of said first bus, said swap means coupled between said first portion of said second bus and said second portion of said first bus, whereby a circuit is devised for selectively trans-ferring bytes and words of digital information to permit a computer organization compatible with the concurrent processing of both byte and word length digital information.

2. The circuit of claim 1 wherein said first and second portions of said digital information comprise eight bits each.

3. The circuit of claim 1 wherein said first means, second means, and swap means are selectively enabled by an enabling signal and one signal communicated on said second bus.

4. The circuit of claim 3 wherein said one signal is the lowest order address signal on said second bus.

5. The circuit of claim 1 wherein said swap means is coupled between said first and second portions of said first bus and is coupled to said first means to transfer said second portion of said digital information therethrough between said first portion of said second bus and said second portion of said first bus.

6. The circuit of claim 1 wherein said swap means is directly coupled between said second portion of said first bus and said first portion of said second bus.

7. A circuit for bidirectionally and selectively trans-ferring bytes and words of digital information between a local and. system bus, each said local and system bus having lower and upper portions, comprising:
a lower transceiver circuit and buffer for bidirectionally and selectively transferring said digital information between said lower portions of said local and system busses, said lower transceiver circuit coupled to lower portions of said local and system busses;
an upper transceiver circuit and buffer for bi-directionally and selectively transferring said digital information between said upper portions of said local and system busses, said upper transceiver circuit coupled to said upper portions of said local and system busses;
a swap byte transceiver circuit and buffer for bi-directionally and selectively transferring said digital in-formation between said lower portion of said system bus and said upper portion of said local bus, said swap byte transceiver coupled to said lower and upper portions of said system and local busses,

Claim 7 continued....

whereby a computer system may be organized to selectively communicate in both byte and word quantities.

8. The circuit of claim 7 wherein said swap byte trans-ceiver circuit and buffer is coupled directly between said upper portion of said local bus and said lower portion of said system bus.

9. The circuit of claim 7 wherein said swap byte trans-ceiver circuit and buffer is coupled between said upper portion of said local bus and said lower portion of said local bus to communicate with said lower portion of said system bus through said lower transceiver circuit and buffer.

10. The circuit of claim 7 wherein said lower, upper and swap byte transceiver circuits and buffers are selectively enabled in response to an external discrete command signal, BHEN, and in response to the least significant bit, ADRO, on an address bus.

11. A method for bidirectionally transferring information between a local and system bus so that the system bus can per-mit compatible transfers in both byte and word quantity lengths, each said local and system bus having a lower and upper portion, comprising the steps of:
decoding a discrete command signal, BHEN, and a least significant address bit, ADRO, on one of said system or local busses to generate a plurality of chip select signals, at least one of said plurality of chip select signals being indicative of a transfer of said information between said lower portion of said system bus and said upper portion of said local bus; and

Claim 11 continued...

selectively enabling a plurality of transceiver circuits to selectively and bidirectionally transfer said information between said upper and lower portions of said local and system bus, at least one of said plurality of transceiver circuits being selectively enabled to perform said transfer of said information between said lower portion of said system bus and said upper portion of said local bus to transfer in-formation between said upper portion of said local bus and said lower portion of said system bus.

12. The method of claim 11 wherein said at least one transceiver is coupled directly between said upper portion of said local bus and said lower portion of said system bus.

13. The method of claim 11 wherein said at least one transceiver is coupled between said upper and lower portions of said local bus to communicate with said lower portion of said system bus through a transceiver coupled directly between said lower portions of said local and system bus.