JPS58144938U - Clock disconnection detection circuit - Google Patents
Clock disconnection detection circuitInfo
- Publication number
- JPS58144938U JPS58144938U JP4028682U JP4028682U JPS58144938U JP S58144938 U JPS58144938 U JP S58144938U JP 4028682 U JP4028682 U JP 4028682U JP 4028682 U JP4028682 U JP 4028682U JP S58144938 U JPS58144938 U JP S58144938U
- Authority
- JP
- Japan
- Prior art keywords
- clock pulse
- detection circuit
- disconnection detection
- input
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title claims description 5
- 238000009499 grossing Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のクロック断検出回路の構成図、第２図は
本考案に係るクロック断検出回路の構成図、第３図は第
２図の各部の波形図である。
Ｅｘ、 ＯＲ・・・クロックパルス有無識別信号形成論
理ゲート、Ｄ工、Ｄ２・・・整流回路、Ｒ１，Ｒ２・・
・放電回路、Ｃ１，Ｃ２・・・平滑回路。FIG. 1 is a block diagram of a conventional clock cutoff detection circuit, FIG. 2 is a block diagram of a clock cutoff detection circuit according to the present invention, and FIG. 3 is a waveform diagram of each part of FIG. 2. Ex, OR...Clock pulse presence/absence identification signal forming logic gate, D, D2... Rectifier circuit, R1, R2...
-Discharge circuit, C1, C2...smoothing circuit.
Claims (1)
クパルスにもとづいて形成されるクロックパルス有無識
別信号を出力とし、単独のクロックパルスが入力された
か否かを検出するクロック断検出回路において、クロッ
クパルス有無識別信号を形成するための論理ゲートが設
けられ、該クロックパルス有無識別信号形成論理ゲート
の入力側には互いに逆特性の整流回路と平滑回路が２つ
ずつ設けられ更に上記各整流回路には放電回路が並列に
接続されていることを特徴とするクロック断検出回路。In a clock disconnection detection circuit that receives a single clock pulse as an input, outputs a clock pulse presence/absence identification signal formed based on the input clock pulse, and detects whether or not a single clock pulse is input. A logic gate for forming a clock pulse presence/absence identification signal is provided, and two rectifying circuits and two smoothing circuits having mutually opposite characteristics are provided on the input side of the clock pulse presence/absence identification signal forming logic gate. A clock disconnection detection circuit characterized in that discharge circuits are connected in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4028682U JPS58144938U (en) | 1982-03-24 | 1982-03-24 | Clock disconnection detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4028682U JPS58144938U (en) | 1982-03-24 | 1982-03-24 | Clock disconnection detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58144938U true JPS58144938U (en) | 1983-09-29 |
Family
ID=30051517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4028682U Pending JPS58144938U (en) | 1982-03-24 | 1982-03-24 | Clock disconnection detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58144938U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489834A (en) * | 1987-09-30 | 1989-04-05 | Nec Corp | Clock input circuit |
-
1982
- 1982-03-24 JP JP4028682U patent/JPS58144938U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489834A (en) * | 1987-09-30 | 1989-04-05 | Nec Corp | Clock input circuit |
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