JPS59138927U - clock switching circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional clock switching circuit.
FIG. 2 is a block diagram showing an embodiment of the clock switching path according to the present invention, and FIGS. 3A to 3E and FIGS. 4a and 4b are time charts showing its operation. 1... Clock disconnection detection circuit, 2... Selection circuit, 3.
...Differentiating circuit, 4...Switching determination circuit, 5, 6...Delay circuit.

Claims (1)

[Scope of utility model registration request] a first delay circuit that provides a predetermined delay to an external clock; a second delay circuit that provides a predetermined delay to the output of the first delay circuit; and an inverted version of the output of the second delay circuit; A differentiation circuit that obtains a differential output by performing an OR with an external clock; a clock interruption detection circuit that detects interruption of the external clock; and the output of this detection circuit and the differential output are input to each of two flip-flops. Assuming that an internal clock is used as a timing input for each of the flip-flops, a switching judgment circuit that performs a switching judgment by identifying the contents of the data input at the rising edge of this timing input; 1. A clock switching circuit comprising a selection circuit that selects and outputs one of the clock applied from the output of the delay circuit and the internal clock.