JPS60170781U - signal detection device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

Fig. 1 is a block configuration diagram showing an example of a conventional signal detection device, Fig. 2 is a diagram showing the operation of Fig. 1 on a time axis, and Fig. 3 shows an example of a signal detection device according to the present invention. Figure 4 is a diagram showing the operation of Figure 3 on the time axis, where 1 is a timing circuit, 2 is a first delay circuit, 3 is a subtracter, 4 is a second delay circuit, and 5 is a diagram showing the operation of Figure 3 on a time axis. Comparator, 6 is accumulator, 7 is multiplier, 8 is buffer register, 9 is selector 2-
Ru. It should be noted that the same or equivalent parts in the figures are indicated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] a first delay circuit and a second delay circuit that delay an input signal; a subtracter that subtracts the output of the first delay circuit from the input signal; and an accumulator that accumulates the output of the subtracter. , a multiplier that multiplies the output of this accumulator by a constant, a buffer register that buffers the output of this multiplier, a selector that selects the output of this buffer register and the output of the multiplier, and the output of this selector. , and a comparator for comparing the amplitude with the output of the second delay circuit.