JPS63139653U - - Google Patents
Info
- Publication number
- JPS63139653U JPS63139653U JP3271187U JP3271187U JPS63139653U JP S63139653 U JPS63139653 U JP S63139653U JP 3271187 U JP3271187 U JP 3271187U JP 3271187 U JP3271187 U JP 3271187U JP S63139653 U JPS63139653 U JP S63139653U
- Authority
- JP
- Japan
- Prior art keywords
- data
- input
- bus
- output
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Bus Control (AREA)
Description
第１図ａはこの考案の一実施例に係るマイクロ
プロセツサのデータ転送回路の構成図、同図ｂは
データ変換回路３の動作を説明する為のタイミン
グチヤート、第２図は本実施例の動作を説明する
フローチヤート、第３図は１６ビツトマイクロプ
ロセツサのバス系統回路図、第４図は一般１６ビ
ツトマイクロプロセツサのデータ転送動作を説明
するフローチヤートである。
図において、１はＣＰＵユニツト、１ａはマイ
クロプロセツサ、１ｂはデバイスメモリ、２は入
出力ユニツト、ＤＢ１，ＤＢ２はデータバス、Ｄ
Ｂ１′は入出力用データバス、ＣＤ′は入出力装
置用コントロールバス、３はデータ変換回路。
FIG. 1a is a block diagram of a data transfer circuit of a microprocessor according to an embodiment of this invention, FIG. 1b is a timing chart for explaining the operation of the data conversion circuit 3, and FIG. FIG. 3 is a bus system circuit diagram of a 16-bit microprocessor, and FIG. 4 is a flowchart explaining the data transfer operation of a general 16-bit microprocessor. In the figure, 1 is a CPU unit, 1a is a microprocessor, 1b is a device memory, 2 is an input/output unit, DB1 and DB2 are data buses,
B1' is an input/output data bus, CD' is a control bus for input/output devices, and 3 is a data conversion circuit.
Claims (1)
置間で授受されるワード構成データ転送するデー
タバスを備えると共に、該データバスを介して入
出力装置へ転送されるワード構成データを２バイ
ト構成のシリアルデータに変換後入出力用データ
バスに転送し、各バイトデータ転送毎に、制御信
号を入出力装置用コントロールバスを介し入出力
装置へ転送するデータ変換回路を備えたことを特
徴とするマイクロプロセツサのデータ転送回路。 It is equipped with a data bus that transfers word configuration data exchanged between the microprocessor and memory and between input/output devices, and converts the word configuration data transferred to the input/output devices via the data bus into 2-byte serial data. A microprocessor characterized in that it is equipped with a data conversion circuit that converts the data into an input/output data bus and transfers the control signal to the input/output device via the input/output device control bus for each byte data transfer. data transfer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3271187U JPS63139653U (en) | 1987-03-06 | 1987-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3271187U JPS63139653U (en) | 1987-03-06 | 1987-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63139653U true JPS63139653U (en) | 1988-09-14 |
Family
ID=30839652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3271187U Pending JPS63139653U (en) | 1987-03-06 | 1987-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63139653U (en) |
-
1987
- 1987-03-06 JP JP3271187U patent/JPS63139653U/ja active Pending
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