JPS61172346U - - Google Patents

Info

Publication number
JPS61172346U
JPS61172346U JP5420885U JP5420885U JPS61172346U JP S61172346 U JPS61172346 U JP S61172346U JP 5420885 U JP5420885 U JP 5420885U JP 5420885 U JP5420885 U JP 5420885U JP S61172346 U JPS61172346 U JP S61172346U
Authority
JP
Japan
Prior art keywords
external memory
wiring
data processing
memory device
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5420885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5420885U priority Critical patent/JPS61172346U/ja
Publication of JPS61172346U publication Critical patent/JPS61172346U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案による外部メモリｉ／Ｆと外部
ｉ／Ｆの一実施例を示す回路ブロツク図、第２図
は本考案の一実施例を示すデータ処理システムの
構成ブロツク図、第３図は第１図の回路動作を説
明するためのタイムチヤートである。 １：ＣＰＵ装置、２：外部メモリ装置、１１：
外部メモリｉ／Ｆ、１１―１，２１―１：インバ
ータ回路、１２，２２：ＣＰＵ、１３，２３：Ｒ
ＡＭ、１４，２４：ＲＯＭ、１５：ＳｉＦ、２１
：外部ｉ／Ｆ、ＣＮ：コネクタ。 FIG. 1 is a circuit block diagram showing an embodiment of an external memory I/F and an external I/F according to the present invention, FIG. 2 is a configuration block diagram of a data processing system showing an embodiment of the present invention, and FIG. 3 is a time chart for explaining the operation of the circuit shown in FIG. 1: CPU device, 2: External memory device, 11:
External memory I/F, 11-1, 21-1: Inverter circuit, 12, 22: CPU, 13, 23: R
AM, 14, 24: ROM, 15: SiF, 21
: External i/F, CN: Connector.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データ処理を行うＣＰＵ装置と、上記データを
記憶する外部メモリ装置と、上記両装置間を配線
で接続するコネクタとを有するデータ処理システ
ムにおいて、上記コネクタの接続作業中に、上記
外部メモリ装置の回路動作を停止させる信号線を
上記配線に具備することを特徴とする外部メモリ
接続装置。 In a data processing system having a CPU device that performs data processing, an external memory device that stores the data, and a connector that connects the two devices by wiring, the circuit of the external memory device is An external memory connection device characterized in that the wiring is provided with a signal line for stopping the operation.
JP5420885U 1985-04-11 1985-04-11 Pending JPS61172346U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5420885U JPS61172346U (en) 1985-04-11 1985-04-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5420885U JPS61172346U (en) 1985-04-11 1985-04-11

Publications (1)

Publication Number Publication Date
JPS61172346U true JPS61172346U (en) 1986-10-25

Family

ID=30575762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5420885U Pending JPS61172346U (en) 1985-04-11 1985-04-11

Country Status (1)

Country Link
JP (1) JPS61172346U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01147711A (en) * 1987-12-04 1989-06-09 Fuji Electric Co Ltd Card equipment mountable with hot-line
JPH02133733U (en) * 1989-04-10 1990-11-06
JPH04199316A (en) * 1990-11-29 1992-07-20 Fujitsu Ltd Information storage device
JPH10320087A (en) * 1997-05-22 1998-12-04 Fujitsu Ltd Connection unit having disk power supply control function

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01147711A (en) * 1987-12-04 1989-06-09 Fuji Electric Co Ltd Card equipment mountable with hot-line
JPH02133733U (en) * 1989-04-10 1990-11-06
JPH04199316A (en) * 1990-11-29 1992-07-20 Fujitsu Ltd Information storage device
JPH10320087A (en) * 1997-05-22 1998-12-04 Fujitsu Ltd Connection unit having disk power supply control function

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