JPS6353151U - - Google Patents

Info

Publication number
JPS6353151U
JPS6353151U JP14350686U JP14350686U JPS6353151U JP S6353151 U JPS6353151 U JP S6353151U JP 14350686 U JP14350686 U JP 14350686U JP 14350686 U JP14350686 U JP 14350686U JP S6353151 U JPS6353151 U JP S6353151U
Authority
JP
Japan
Prior art keywords
data
control signal
block
ready
transfer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14350686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14350686U priority Critical patent/JPS6353151U/ja
Publication of JPS6353151U publication Critical patent/JPS6353151U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案に係るデータ転送システムの
一実施例を示すブロツク回路図、第2図は同実施
例の動作サイクルを説明するための図、第3図は
従来のコンピユータシステムのデータ転送手段を
説明するためのブロツク回路図、第4図は従来シ
ステムの動作サイクルを説明するための図である
。 1…CPU、2…RAM、3,4…アドレスデ
コーダ、5…ラツチ、6…外部インターフエース
、7…データバス、8…アドレスバス、9…NA
NDゲート、9′…インバータ、10,11…N
ORゲート。
Fig. 1 is a block circuit diagram showing an embodiment of the data transfer system according to this invention, Fig. 2 is a diagram for explaining the operation cycle of the same embodiment, and Fig. 3 is a data transfer means of a conventional computer system. FIG. 4 is a block circuit diagram for explaining the operation cycle of the conventional system. 1...CPU, 2...RAM, 3, 4...Address decoder, 5...Latch, 6...External interface, 7...Data bus, 8...Address bus, 9...NA
ND gate, 9'...inverter, 10, 11...N
OR gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] コンピユータのデータを送出するブロツクを送
出可能状態にする制御信号とデータを受信するブ
ロツクを受信可能状態にする制御信号を同時に発
生する回路を具備し、前記ブロツク間のデータ転
送をひとつの命令単位で行うデータ転送システム
It is equipped with a circuit that simultaneously generates a control signal that makes a block that sends computer data ready for sending, and a control signal that makes a block that receives data ready for receiving data, and transfers data between the blocks in one command unit. data transfer system.
JP14350686U 1986-09-19 1986-09-19 Pending JPS6353151U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14350686U JPS6353151U (en) 1986-09-19 1986-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14350686U JPS6353151U (en) 1986-09-19 1986-09-19

Publications (1)

Publication Number Publication Date
JPS6353151U true JPS6353151U (en) 1988-04-09

Family

ID=31053254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14350686U Pending JPS6353151U (en) 1986-09-19 1986-09-19

Country Status (1)

Country Link
JP (1) JPS6353151U (en)

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