JPH0486948U - - Google Patents
Info
- Publication number
- JPH0486948U JPH0486948U JP12641290U JP12641290U JPH0486948U JP H0486948 U JPH0486948 U JP H0486948U JP 12641290 U JP12641290 U JP 12641290U JP 12641290 U JP12641290 U JP 12641290U JP H0486948 U JPH0486948 U JP H0486948U
- Authority
- JP
- Japan
- Prior art keywords
- input
- data bus
- output device
- package
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 238000003745 diagnosis Methods 0.000 description 1
Landscapes
- Detection And Correction Of Errors (AREA)
Description
第１図は本考案の一実施例のパツケージ内部の
ブロツク図、第２図は第１図のパツケージを実装
するうえでのシステム構成図、第３図は従来のパ
ツケージのブロツク図である。
１……入出力装置、２……コントローラ、６…
…入出力パツケージ、７……インターフエースパ
ツケージ、１０……パツケージのメモリＦＩＦＯ
、１１……入力データ（８ｂｉｔ）、１２……診
断ビツト、１３……コントロールビツト、１４…
…ワンチツプマイコン、１５……パツケージ内部
のデータバス、１６……チエツク回路、１７……
ＭＰＵに知らせる信号、１８……ケージ内のデー
タバス、１９……入出力制御回路。
FIG. 1 is a block diagram of the inside of a package according to an embodiment of the present invention, FIG. 2 is a system configuration diagram for implementing the package of FIG. 1, and FIG. 3 is a block diagram of a conventional package. 1... Input/output device, 2... Controller, 6...
...I/O package, 7...Interface package, 10...Package memory FIFO
, 11... Input data (8 bits), 12... Diagnosis bit, 13... Control bit, 14...
...One-chip microcontroller, 15... Data bus inside the package, 16... Check circuit, 17...
Signal to inform MPU, 18...data bus in cage, 19...input/output control circuit.
Claims (1)
抜する際、データバスが揺さぶられ、別のパツケ
ージに影響を与え、入出力装置内はパラレルバス
のＣＰＵによる通信を行ない、ハード的に診断ビ
ツトを付加し、それをＣＰＵが正当性を判断する
ことを特徴とする入出力装置のデータバス。 When inserting or removing a package in an input/output device that is energized, the data bus is shaken, affecting other packages, and the input/output device communicates using the parallel bus CPU, adding diagnostic bits to the hardware. A data bus of an input/output device characterized in that a CPU judges the validity of the data bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12641290U JPH0486948U (en) | 1990-11-30 | 1990-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12641290U JPH0486948U (en) | 1990-11-30 | 1990-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0486948U true JPH0486948U (en) | 1992-07-28 |
Family
ID=31873971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12641290U Pending JPH0486948U (en) | 1990-11-30 | 1990-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0486948U (en) |
-
1990
- 1990-11-30 JP JP12641290U patent/JPH0486948U/ja active Pending
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