JPH0196061U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image compression apparatus of this invention, and FIG. 2 is a block diagram showing a conventional image compression apparatus. In the figure, 1 is a CPU, 2 is a memory controller, 3 is an image memory, 4 is a compression section, 5 is a buffer, 6 is a processor, 7 is an interface, and 8 is a bus. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] A CPU that controls and manages the entire device, a memory controller that controls input/output and transfer of image data, an image memory that stores image data under the control of this memory controller, and a computer that stores image data in this image memory. a compression unit that performs calculations, conversion, etc. on the image data in order to compress the image data, and an interface that transmits instructions when a person or a computer serving as a host gives instructions to the device; In an image compression device that is equipped with a bus that connects each part of these devices, the compression section is equipped with a buffer that stores part of the image data and a dedicated processor that performs calculations, conversion, etc. for compression. An image compression device characterized by: