JPS63179504U - - Google Patents
Info
- Publication number
- JPS63179504U JPS63179504U JP7081387U JP7081387U JPS63179504U JP S63179504 U JPS63179504 U JP S63179504U JP 7081387 U JP7081387 U JP 7081387U JP 7081387 U JP7081387 U JP 7081387U JP S63179504 U JPS63179504 U JP S63179504U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output device
- controlling
- control device
- command signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Numerical Control (AREA)
- Communication Control (AREA)
Description
第１図はこの考案の一実施例による数値制御装
置とホスト・コンピユータの関連を示すブロツク
図、第２図はこの考案の一実施例による数値制御
装置に設けられた電話回線とのインターフエイス
を示す模式図、第３図は従来の数値制御装置とホ
スト・コンピユータとの関連を示すブロツク図で
ある。
図において、１５はＣＰＵ、１６は入出力装置
、１７は補助のメモリ装置、１８はＤＭＡ装置、
１９はメモリ装置を示す。なお、図中、同一符号
は同一、または相当部分を示す。
Fig. 1 is a block diagram showing the relationship between a numerical control device according to an embodiment of this invention and a host computer, and Fig. 2 shows an interface with a telephone line provided in a numerical control device according to an embodiment of this invention. The schematic diagram shown in FIG. 3 is a block diagram showing the relationship between a conventional numerical control device and a host computer. In the figure, 15 is a CPU, 16 is an input/output device, 17 is an auxiliary memory device, 18 is a DMA device,
19 indicates a memory device. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
線を介して送受信され、上記指令信号を入出力す
る入出力装置と、この入出力装置により受信され
た信号をメモリ装置に直接転送する制御装置と、
上記入出力装置を制御するデータを格納しておく
補助のメモリ装置とを備えたことを特徴とする数
値制御装置。 A command signal for controlling a controlled object is transmitted and received via a telephone line, and an input/output device inputs and outputs the command signal, and a control device directly transfers the signal received by the input/output device to a memory device. and,
A numerical control device characterized by comprising an auxiliary memory device for storing data for controlling the input/output device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7081387U JPS63179504U (en) | 1987-05-12 | 1987-05-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7081387U JPS63179504U (en) | 1987-05-12 | 1987-05-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63179504U true JPS63179504U (en) | 1988-11-21 |
Family
ID=30912790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7081387U Pending JPS63179504U (en) | 1987-05-12 | 1987-05-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63179504U (en) |
-
1987
- 1987-05-12 JP JP7081387U patent/JPS63179504U/ja active Pending