JPS5847940U - automatic data acquisition device - Google Patents

automatic data acquisition device

Info

Publication number
JPS5847940U
JPS5847940U JP14366181U JP14366181U JPS5847940U JP S5847940 U JPS5847940 U JP S5847940U JP 14366181 U JP14366181 U JP 14366181U JP 14366181 U JP14366181 U JP 14366181U JP S5847940 U JPS5847940 U JP S5847940U
Authority
JP
Japan
Prior art keywords
bus
power supply
data acquisition
data
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14366181U
Other languages
Japanese (ja)
Other versions
JPS616512Y2 (en
Inventor
田辺　共之
Original Assignee
中浅測器株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中浅測器株式会社 filed Critical 中浅測器株式会社
Priority to JP14366181U priority Critical patent/JPS5847940U/en
Publication of JPS5847940U publication Critical patent/JPS5847940U/en
Application granted granted Critical
Publication of JPS616512Y2 publication Critical patent/JPS616512Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案実施例装置のブロック構成図。　′１・・・
データバス、２・・・マイクロプロセッサ、３・・・読
出し専用メモリ（ＲＯＭ）、４・・・書込み読出しメモ
！Ｊ　（ＲＡＭ）、５・・・表示制御パネル部、６・・
・時計回路、７・・・バス電源制御回路、８・・・バッ
テリ、１０・・・データバス、１１・・・読出し専用メ
モリ（ＲＯＭ）、１２・・・書込み読出しメモリ（ＲＡ
Ｍ）、１３・・・入力インタフェース、１４・・・出力
インタフェース、１６・・・バススイッチング部、１７
・・・電源開閉回路、１８・・・バッテリ。The figure is a block configuration diagram of an apparatus according to an embodiment of the present invention. '1...
Data bus, 2...Microprocessor, 3...Read-only memory (ROM), 4...Write/read memo! J (RAM), 5...Display control panel section, 6...
・Clock circuit, 7... Bus power control circuit, 8... Battery, 10... Data bus, 11... Read only memory (ROM), 12... Write/read memory (RA
M), 13... Input interface, 14... Output interface, 16... Bus switching section, 17
...Power switching circuit, 18...Battery.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第一のデータバスに、データ集録動作を制御するマイク
ロプロセッサと、このマイクロプロセッサが常時動作す
るために必要なプログラムが書込まれた第一のメモリと
、クロック信号に従って制御信号を検出するバス電源制
御回路とが接続され、第二のデータバスに、上記マイク
ロプロセッサのデータ集録動作の制御に必要なプログラ
ムが書込まれた第二のメモリと、データ集録回路に接続
されるインタフェースとが接続され、上記第一のデータ
バスと上記第二のデータバスとの間に設けられ両データ
バスの信号通路を上記バス電源側゛御回路より送出され
る制御信号により開閉するバススイッチレグ部を備え、
上記第二のデータバスに接続、された各装置の電源回路
を上記バス電源制御回路より送出される制御信号により
開閉する電源開閉回路を備えた自動データ集録装置。A first data bus includes a microprocessor that controls data acquisition operations, a first memory in which programs necessary for this microprocessor to operate at all times are written, and a bus power supply that detects control signals according to a clock signal. A second memory, in which a program necessary for controlling the data acquisition operation of the microprocessor is written, and an interface connected to the data acquisition circuit are connected to the second data bus. , comprising a bus switch leg section provided between the first data bus and the second data bus, which opens and closes the signal paths of both data buses in response to a control signal sent from the bus power supply side control circuit,
An automatic data acquisition device comprising a power supply switching circuit that opens and closes a power supply circuit of each device connected to the second data bus in accordance with a control signal sent from the bus power supply control circuit.
JP14366181U 1981-09-28 1981-09-28 automatic data acquisition device Granted JPS5847940U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14366181U JPS5847940U (en) 1981-09-28 1981-09-28 automatic data acquisition device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14366181U JPS5847940U (en) 1981-09-28 1981-09-28 automatic data acquisition device

Publications (2)

Publication Number Publication Date
JPS5847940U true JPS5847940U (en) 1983-03-31
JPS616512Y2 JPS616512Y2 (en) 1986-02-27

Family

ID=29936640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14366181U Granted JPS5847940U (en) 1981-09-28 1981-09-28 automatic data acquisition device

Country Status (1)

Country Link
JP (1) JPS5847940U (en)

Also Published As

Publication number Publication date
JPS616512Y2 (en) 1986-02-27

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