JPH06180987A - Decoder circuit - Google Patents

Abstract

PURPOSE:To provide a decoder circuit which makes multi-selection unnecessary. CONSTITUTION:This decoder circuit is provided with the main body D of a decoder circuit for decoding a plurality of addresses, an address transition detecting circuit 16 for detecting the transition of addresses to generate a signal 5 for a fixed period of time and deactivate the main body D of a decoder circuit by the signal 5. Since the transition of addresses is completed within the period of time when the main body D of a decoder circuit is deactivated by the signal 5 which the address transition detecting circuit 16 generates, decoding is possible without the need of multi-selection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder circuit.

[0002]

2. Description of the Related Art Conventionally, a decoder circuit has been composed of a NAND circuit or a NOR circuit which receives only an address signal as an input signal. A decoder circuit using a conventional NAND circuit is shown in FIG. This decoder circuit is composed of four NAND circuits 23 to 26, and four kinds of signals 6, 7, 9, 10 generated from two address signals 8, 11 are input to each NAND circuit. . Here, the signals 6 and 7 are signals generated from the same address signal 8 and opposite in phase to each other, and the signals 9 and 10 are signals generated from the same address signal 11 and opposite in phase to each other. The buffer circuits 17 and 18 receive the address signal 8 to the signal 6, respectively.
7, the buffer circuits 19 and 20 generate signals 9 and 10 from the address signal 11. The address signal 8 is generated from the address input terminal 27 through the address input buffer circuit 28. The address signal 11 is generated from the address input terminal 29 through the address input buffer circuit 30. In addition, the first input to each of the NAND circuits 23 to 26
And the second two signals are of course different address signals 8,
The signals generated by 11 are input. For example, signals 6 and 9 are input to the NAND circuit 23. The signals 12 to 15 are output signals of the NAND circuits 23 to 26, respectively. The operation will be described below.

The output signal from the NAND circuit is L only when all the signals input to the NAND circuit become H.
Becomes For example, if the signals 6 and 9 are H, only the output signal 12 from the NAND circuit 23 is L. The other three N
The outputs of the AND circuits 24, 25 and 26 are the respective NANs.
Signal 6 and signal 1 input to D circuits 24, 25, 26
0, the signal 7 and the signal 9, and the signal 7 and the signal 10 are input to the NAND circuits 24, 25, and 26 so that at least one of the two signals of the three sets is L. 15 becomes H.

[0004]

When the distance between the address input buffer circuit and the decoder circuit is large, the wiring capacitance and wiring resistance of the signal line become large. Therefore, the buffer circuits 17 and 18 are placed between the address signal 8 and the signals 6 and 7, but in such a state, the signals 6 and 7, which are signals generated from the same address signal 8 and having opposite phases to each other, are not always available. Do not make transitions at the same timing. That is, the time when the signal 6 changes from H to L and the time when the signal 7 changes from L to H do not necessarily match. The timing chart at this time is shown in FIG. Hereinafter, FIG. 3 will be described.

Normally, the two signals input to the NAND circuits 23 to 26 are both H, and there are four NAND circuits.
There is only one of the circuits 23 to 26, but in this case, it is possible that two or more address transitions exist in the period until the transition is completed. That is, the output signals of two or more NAND circuits may be simultaneously set to L, and multiple selection may occur. For example, when the address signal 8 is from L to H
, The signal 6 goes from L to H and the signal 7 goes from H to L. Here, compared to the case where the signal 6 changes from L to H, the signal 7
Is delayed from H to L, the NAND circuit 23,
A period in which the 25 output signals 12 and 14 are simultaneously at L occurs, and multiple selection occurs.

An object of the present invention is to provide a decoder circuit in which multiple selection does not occur.

[0007]

According to a first aspect of the present invention, there is provided a decoder circuit main body for decoding a plurality of addresses, a signal is generated for a certain period of time by detecting a transition of the address, and the decoder circuit main body is deactivated by this signal. And an address transition detection circuit for activation. A decoder circuit according to claim 2, wherein a decoder circuit body for decoding a plurality of addresses, a circuit for generating a signal for controlling address fetching, and a signal for deactivating the decoder circuit body from the signal for controlling address fetching. And a circuit for generating.

[0008]

According to the structure of the present invention, since the address transition is completed while the decoder circuit body is inactivated by the signal for inactivating the decoder circuit body, decoding can be performed without multiple selection.

[0009]

1 is a circuit diagram of a decoder circuit according to a first embodiment of the present invention. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals. This decoder circuit includes a decoder circuit body D and an address transition detection circuit 16. The decoder circuit body D is composed of four 3-input NAND circuits 1, 2, 3, and 4. Address transition detection circuit 1
The signal 5 from 6 is input to all four NAND circuits 1, 2, 3, 4. Signals 6 and 7 are signals which are generated from the address signal 8 and have opposite phases. Similarly, signals 9 and 10 are generated from address signal 11 and have opposite phases. Signal 6,
Each of the four kinds of signals obtained by selecting one signal from 7 and one signal from 9 and 10 has four NANs.
It is input to the remaining two inputs of the D circuits 1, 2, 3, and 4. Signals 12, 13, 14, 15 are NAND circuits 1,
These are output signals 2, 3, and 4, respectively. The address transition detection circuit 16 detects the transition of the address signals 8 and 11 and generates the signal 5. The circuits 17, 18, 19, and 20 are examples of buffer circuits that generate and amplify the signals 6, 7, 9, and 10 from the address signals 8 and 11.

The operation of this decoder circuit will be described below. FIG. 3 shows an example of a timing chart of the decoder circuit shown in FIG. Address signal 8
Signal changes from H to L, signal 6 changes from H to L
Changes from L to H. It is assumed that the address signal 9 remains H and does not transit. At this time, it is assumed that the signal 6 is behind the signal 7. In this case, in the conventional system shown in FIG. 4, there is a period 21 in which the outputs 12 and 14 from the NAND circuit are at L at the same time, and multiple selection occurs. However, in this decoder circuit, during the period 21, since the signal 5 is L, the outputs 12, 13, 14, 15 of the NAND circuit are all H. After that, when the signal 5 becomes H, the output 14 of the NAND circuit becomes L, and at the same time, the outputs of two or more 3-input NAND circuits become L, so that the multiple selection does not occur.

Although the above description has been made with respect to the decoder circuit using the NAND circuit, it goes without saying that the same thing is valid for the NOR circuit. Of course, in the NOR circuit, H is output as an output signal when all the input signals are L. Therefore, the third signal input to the NOR circuit may be in the opposite phase to the signal 5 input in the case of the NAND circuit. In the above description, the address transition detection circuit 16 is used as the third signal.
Although the signal 5 from the NAND circuit 1 is used, the same effect is obtained by using another clock signal to generate a signal similar to the signal 5.
You can get it by typing in ~ 4. For example, a second embodiment will be described with reference to FIG.

FIG. 2 is a circuit diagram of a decoder circuit according to the second embodiment of the present invention. 2, parts corresponding to those in FIGS. 1 and 4 are designated by the same reference numerals. In this decoder circuit, the address transition occurs when a new address signal is fetched, so the timing of fetching the input address signal is determined by another signal 22, and a signal similar to the signal 5 in FIG. Take the structure to create. That is, the signal 22 is generated by the clock generation circuit 31, and the address input buffer circuit 28,
30 is controlled, the address signal is taken in, and the signal 33 is generated by the signal generating circuit 32.
The signal 33 functions similarly to the signal 5 in FIG.

Needless to say, the same applies to a multi-input NAND circuit or NOR circuit having four or more inputs as well as three inputs. Also, the same NAN as the conventional example
A configuration may be used in which a NOR circuit or a NAND circuit which uses the D circuit or the NOR circuit and inputs the output signal and the control signal is provided.

[0014]

As described above, according to the decoder circuit of the present invention, since the address transition is completed while the decoder circuit body is inactivated by the signal for inactivating the decoder circuit body, multiple selection is performed. Can be decoded without.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a decoder circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a decoder circuit according to a second embodiment of the present invention.

FIG. 3 is a timing chart of a decoder circuit.

FIG. 4 is a circuit diagram of a conventional decoder circuit.

[Explanation of symbols]

 D Decoder circuit body 1 to 4 NAND circuit 5 signal 6,7,9,10 Input signal to NAND circuit 8,11 Address signal 12 to 15 NAND circuit output signal 16 Address transition detection circuit 17 to 20 Buffer circuit 21 Period 22 Signals 23 to 26 NAND circuit 27, 29 Address input terminal 28, 30 Address input buffer circuit 31 Clock generation circuit 32 Signal generation circuit 33 Signal

Claims (2)

[Claims] 1. A decoder circuit main body for decoding a plurality of addresses, and an address transition detection circuit for detecting a transition of the address, generating a signal for a certain period of time, and deactivating the decoder circuit main body by this signal. Decoder circuit. 2. A decoder circuit body for decoding a plurality of addresses, a circuit for generating a signal for controlling the fetching of the address, and a signal for deactivating the decoder circuit body from the signal for controlling the fetching of the address. A decoder circuit having a generating circuit.