JP2005251112A - Clock switching circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock switching circuit capable of switching a plurality of input clocks by a clock switching signal generated outside or inside an information processor without initializing a device, and causing no hazard during clock switching. <P>SOLUTION: In the clock switching circuit selecting and outputting one optional clock as an output clock out of at least two input clocks on the basis of a clock selection input signal, a clock selecting means for generating the output clock is provided by a selection signal storing part synchronizing with the output clock and acquiring the clock selection input signal, a switching signal generating part for decoding an output of the selection signal storing part and specifying the output clock, and a switching enabling part provided per each input clock, acquiring an output of the switching signal generating part in synchronization with the input clock, and outputting an enabling signal for outputting the input clock as the output clock. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a clock switching circuit in an information processing device using a clock of a communication device, a video device, a computer, etc., and the clock to be switched is a plurality of synchronous or asynchronous, further arbitrary duty ratios, information With a clock switching signal generated outside or inside the processing device, it can be switched at any time and at any timing without initializing the device, and a clock switching circuit that does not cause a hazard at the time of clock switching, The present invention relates to a clock switching circuit capable of easily increasing the number of selection target clocks.

  In the conventional clock switching circuit, it is a simple realization method that switching of an arbitrary input clock is performed at a system reset timing. However, there is a strong demand for switching during system startup, and many methods have been proposed. 2 related to clocks having the same clock duty ratio (see Patent Document 1) and those having the same frequency and allowing an arbitrary phase error (refer to Patent Document 2). Although the input can be switched, there are some that cannot easily handle three or more inputs (see Patent Document 3).

JP-A-5-268205 JP 2003-208400 A JP-A-5-268022

  However, in the case of the method of Patent Document 1, since the output of the clock gate means is used as the input of the delay means, there is a condition that the number of input clocks is 2 or less and the duty ratio is equal.

  FIG. 3 is a block diagram of a clock switching circuit as an example of the prior art (see Patent Document 2). In the switching circuit shown in FIG. 3, any input clock can be selected as long as the clocks have the same frequency and an arbitrary phase difference. The input from the switching timing generation unit 301 to the clock switching adjustment unit 302 is generated from a logical sum. Therefore, when the frequencies of the input clocks are different, the period during which the levels of the input clocks are all LOW or HIGH is not guaranteed at all for the required specifications of the input of the clock switching adjustment unit. Further, although the phase difference is arbitrary, when the number of input clocks increases, the period during which all the input clock levels are LOW or HIGH is not guaranteed. Therefore, it is possible to perform good switching only with input clocks having the same frequency, different phase differences, and a small number of input clocks or a small phase difference.

  On the other hand, in the switching method in Patent Document 3, the conditions of Patent Document 1 and Patent Document 2 are improved. That is, in 2-input clock switching, a favorable circuit is provided for switching any clock without conditions such as duty ratio, frequency, and phase. However, no means for realizing the case where the number of clocks to be selected is increased to 3, 4 is presented.

  Therefore, to output any one of three or more selected clocks, for example, reset the system once, switch between them, or reset, but mask all clock inputs for a certain period. It was necessary to switch.

  The present invention has been made in view of the above problems, and its purpose is to provide a plurality of synchronous or asynchronous input clocks having an arbitrary duty ratio by clock switching signals generated outside or inside the information processing apparatus. An object of the present invention is to provide a clock switching circuit which can be switched at an arbitrary time and at an arbitrary timing without initializing the apparatus and does not cause a hazard at the time of clock switching.

In order to solve the above problems, the clock switching circuit according to the present invention is a clock switching circuit that selects and outputs an arbitrary clock as an output clock from a plurality of input clocks based on a clock selection input signal.
A selection signal storage unit that captures the clock selection input signal in synchronization with the output clock;
A switching signal generation unit for decoding the output of the selection signal storage unit and specifying an output clock;
A switching permission unit that is provided for each input clock, outputs a permission signal for capturing the output of the previous switching signal generation unit in synchronization with the input clock, and outputting the input clock as the output clock;
Clock selection means for generating an output clock from a set of outputs of the plurality of switching permission sections and a plurality of input clocks corresponding to each switching permission section.

  In the clock switching circuit, the switching signal generation unit receives the permission signal of another switching signal generation unit, and when there is a permission signal of the other switching signal generation unit, the permission signal of the switching signal generation unit Stop the output of.

  As described above, the clock switching circuit of the present invention has no restrictions on clocks such as synchronous, asynchronous and duty ratio, does not cause a hazard at the time of switching, and further simplifies the number of input clocks to be selected. It is possible to provide a clock switching circuit that can be set to 3 or more.

[Example 1]
Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram of a clock switching circuit according to an embodiment of the present invention.

  A selection signal 109 is input to the clock switching circuit, and the selection signal 109 is input to the selection signal storage unit 100. The output 110 of the selection signal storage unit 100 is input to the switching signal generation unit 101. The switching signal generator 101 outputs selection signals 103a, 103b, 103c, and 103d for selecting any one of clock inputs having different phases and frequencies and external clock inputs of CLK0, CLK1, CLK2, and CLK3. The selection signals 103a to 103d output from the switching signal generation unit 101 are input to the switching permission units 102a, 102b, 102c, and 102d that generate a switching permission signal for the corresponding input clock. The selection signals 103a to 103d and the corresponding clocks CLK0 to CLK3 are input to the switching permission units 102a to 102d. Then, switching permission signals 104a, 104b, 104c, and 104d are generated. On the other hand, the clock permission signal of the switching permission section of another system clock is input to the switching permission section. The switching permission signals 104a to 104d that are the outputs of the switching permission sections 102a to 102d are input to the clock selection section 111 together with the corresponding clocks CLK0 to CLK3, and CLKOUT is output as the clock output. The clock output CLKOUT is inverted by the inverter 108 and supplied as the selection signal fetch clock of the selection signal storage unit 100.

  In the present embodiment, the selection signal 109 is stored in the selection signal storage unit 100 and then input to the switching signal generation unit 101. However, the selection signal 109 is switched to the switching signal. The selection signals 103 a to 103 d that are the outputs of the switching signal generation unit 101 may be input to the selection signal storage unit 100 by being input to the signal generation unit 101. However, in this case, the number of bits of the selection signal storage unit 100 is 4 bits.

  In this embodiment, the selection signal 109 is 2 bits, and the selection signal storage unit 100 is also 2 bits. The selection signal generation unit 100 can be configured with a D-type flip-flop or the like. The selection signal 109 given from the outside is taken into the selection signal storage unit at the falling timing of the CLKOUT and immediately output to the switching signal generation unit 101.

The switching signal generator 101 is a decoder circuit that generates a 4-bit output from a 2-bit input. The switching signal generation unit 101 changes the only one of the selection signals 103a to 103d to an active level according to a combination of 2 bits of the output 110 of the selection signal generation unit 100. (In this embodiment, the active level is the case of being in the HIGH level)
The clock selector 111 receives the CLK0 to CLK3 and the switching permission signals 104a to 104d that are the outputs of the switching permission sections 102a to 102d, and the CLK0 and the switching permission signal 104a are input to the two-input AND gate 105a. Entered. Similarly, the CLK1 and the switching permission signal 104b, the CLK2 and the switching permission signal 104c, and the CLK3 and the switching permission signal 104d are input to the two-input AND gates 105b, 105c, and 105d, respectively. The two-input AND gates 105a to 105d are input to a four-input OR gate 106 to form a selection circuit. Although a 2-input NAD gate and a 4-input OR gate are used here, a 2-input NAND gate and a 4-input NAND gate (that is, a negative input OR gate) may be used.

  The selection signal storage unit 100 is 2 bits in this embodiment, but may be 1 bit, 3 bits or more, and can be set to any bit of 1 bit or more. Further, the switching signal generation unit 101 may be input according to the bit width of the selection signal storage unit 100. That is, when the selection signal storage unit 100 is 1 bit, 1 bit is 2 outputs, when the selection signal storage unit 100 is 2 bits, 2 bits are 4 outputs, and the selection signal storage unit 100 is 3 bits. In the case of bits, there are 3 bits input and 8 outputs.

  FIG. 4 is an internal configuration circuit diagram of the switching signal generator 101. In this embodiment, it is a general 2-bit decoder circuit.

  The 2-bit output 110 of the selection signal storage unit 100 is set to in1 and in2. in1 is input to the inverter 400, and in2 is input to the inverter 401, and an inverted output is generated. A combination of in1, in2 and respective inverted outputs is input to two-input AND gates 402 to 405, and selection signals 103a to 103d are generated.

  FIG. 2 is an internal circuit diagram of the switching permission units 102a and 102b, 102c, and 102d. Here, the switching permission unit 102a for selecting CLK0 will be described. Since the same can be said for the inside of the switching permission units 102b to 102d, description thereof is omitted here.

  A DECn signal is connected to the 2-input AND gate 202, which becomes the selection signal 103a in FIG. The other input of the 2-input AND gate 202 is connected to the output of the negative 3-input AND gate 201. Since the three-input AND gate 201 is a negative input, the output is HIGH when all three inputs are LOW. This is the same function as a 3-input NOR. The inputs of the 3-input AND gate 201 are CLKENi, CLKENj, and CLKENk. These three inputs are outputs 104b to 104d of the switching permission units 102b to 102d for permitting clocks of other systems. The output of the 2-input AND gate 202 is the D input of the D flip-flop 200. The clock input of the D flip-flop 200 is CLKn, that is, CLK0 inverted by the inverter 203. That is, CLKENn is output in synchronization with the falling edge of CLK0. This CLKENn becomes the switching permission signal 104a.

  Next, the operation of the clock switching circuit of the present invention will be described with reference to the timing chart of FIG.

  In the timing chart of FIG. 5, at any time, the selection signal 109 is “00b”, CLK0 is selected and output from the CLKOUT.

  In this state, the selection signal 109 switches to “01b” at time Tc. The selection signal 109 switched at the time Tc is taken into the selection signal storage unit 100 at time T0, which is the falling timing of the CLKOUT.

  The output 110 of the selection signal storage unit 100 is input to the switching signal generation unit 101 and decoded, so that the selection signal 103a, which has been at a high level so far, becomes a low level, and has been at a low level until now. The selection signal 103b becomes HIGH level.

  At this time, the other selection signals 103c and 103d remain at the LOW level.

  The selection signal 103a that has reached the LOW level acts on the selection signal 102a, and at time T1, the switching permission signal 104a that is the output of the selection signal 102a becomes the LOW level.

  At the time T1, the switching permission signal 104a becomes LOW level, so that the output of the 3-input AND gate 201 in FIG. 2 becomes HIGH level. As a result, one input of the two-input AND gate 202 in FIG. 2 becomes HIGH level.

  On the other hand, the other input of the two-input AND gate 202 in FIG. 2 is at a HIGH level after the time T0. Therefore, the output of the two-input AND gate 202 in FIG. 2 becomes HIGH level.

  Therefore, the D flip-flop 200 in FIG. 2 becomes HIGH level at time T2, which is the fall of the CLK1, by the inverter 203 in FIG.

  As a result, at the time T2, the switching permission signal 104b becomes HIGH level.

  When the permission signal 104b becomes HIGH level, one input of the 2-input AND gate 105b in the clock selection unit 111 becomes HIGH, and the other input, CLK1, is output from the 2-input AND gate 105b. Become.

  Here, since only the outputs 103a to 103d of the switching signal generator 101 are HIGH, one of the other two-input AND gates 105a, 105c, and 105d in the clock selector 111 is provided. Input is LOW level. Therefore, the outputs of the two-input AND gates 105a, 105c and 105d are at the LOW level.

  Even when the selection signal 109 is switched from “01b” to “11b” at time Tc2, it is taken into the selection signal storage unit 100 at time T3, and at time T4, as described above. The permission signal 104b of the CLK1 which has been output until becomes the LOW level, and the permission signal 104d of the CLK3 becomes the HIGH level at the time T5 which is the next falling of the CLK3.

  Therefore, at time Tc3, the CLKOUT is switched to the CLK3.

  In the clock switching circuit of the present invention, the output of the CLK0 is prohibited at the time T1, which is the fall of the CLK0. At this time, the switching permission signal 104b of the clock to be switched next is not yet HIGH level. Next, the output of all clocks is prohibited until the switching permission signal 104b becomes HIGH at the time T2, which is the fall of the CLK1 to be switched. With the above operation, it is possible to switch the clock without any hazard.

  Although only the clock switching circuit has been described, the present invention can be applied to all electronic devices using a microcomputer or a CPU that switches and uses a plurality of clocks.

The block diagram explaining one Embodiment of this invention Internal block diagram of an embodiment of the switching permission unit Block diagram of an example of the prior art Internal block diagram of an embodiment of the switching signal generator Timing chart explaining operation of the present invention

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Selection signal memory | storage part, 101 ... Switching signal production | generation part, 102a-102d ... Switching permission part, 103a-103c ... Selection signal, 104a-104d ... Switching permission signal, 105a-105d ... 2 input AND gate, 106 ... 4 input OR gate, 107a to 107d ... CLK0 to CLK3, 108 ... inverter, 109 ... selection signal, 110 selection signal storage unit output, 111 ... Clock selection unit, 200 ... D flip-flop, 201 ... 3 input AND gate, 202 ... 2 input AND gate, 203 ... inverter, 300 ... clock selection unit, 301 ... switching timing Generation unit, 302... Clock switching adjustment unit, 400 to 401... Inverter, 402 to 405... 2 input AND gate

Claims (2)

In a clock switching circuit that selects and outputs an arbitrary clock as an output clock from a plurality of input clocks based on a clock selection input signal,
A selection signal storage unit that captures the clock selection input signal in synchronization with the output clock;
A switching signal generation unit for decoding the output of the selection signal storage unit and specifying an output clock;
A switching permission unit that is provided for each input clock, outputs a permission signal for capturing the output of the previous switching signal generation unit in synchronization with the input clock, and outputting the input clock as the output clock;
Having a clock selection means for generating an output clock from a set of a plurality of outputs and a plurality of input clocks corresponding to each switching permission unit;
A clock switching circuit.   The switching signal generation unit stops the output of the permission signal of the switching signal generation unit when the permission signal of the other switching signal generation unit is input and the permission signal of the other switching signal generation unit exists. The clock switching circuit according to claim 1.

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