JPH0553791A - Control information reader - Google Patents

Abstract

PURPOSE:To read control information at high speed by the two hierarchical control storing system of high-order control storage and low-order control storage. CONSTITUTION:The succeeding address field of control information read from high-order control storage 4 is alternately stored in registers 7 and 8. Control information read from low-order control storage 9 and 10 respectively corresponding to the registers 7 and 8 is alternately switched by a selector 11 so as to be outputted. When control information is being read from one of low- order control storage, the reading of the other low-order control storage can be prepared so as to successively obtain control information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control information reading device, and more particularly to speeding up reading of control information in an information processing device that performs arithmetic control by a microprogram.

[0002]

2. Description of the Related Art Conventionally, in the microprogram system of this type of information processing apparatus, it is desirable to increase the bit width of the microinstruction and store the control signals of many circuits in the microinstruction. The complexity of the device requires very long microinstructions.

Therefore, there is a method of reducing the bit width of a microinstruction by using a so-called control memory in which patterns of control signals of a large number of circuits are stored and the control information is output according to an instruction of the microinstruction. This is called a two-level control storage system, and this control storage is realized by a memory or the like having a field with a microinstruction as an address.

FIG. 8 is a block diagram showing an example of the structure of the two-layer control storage system, and FIG. 11 is a time chart showing the operation of the control information reading device of FIG. The operation of the control information reading device will be described below with reference to FIGS.

The microprogram is started by first storing the address of the microinstruction in the address register 2. The microinstruction stored in the upper control memory 4 is read by the address of the microinstruction in the address register 2. This microinstruction includes a field indicating the address of the next microinstruction when branching, a field indicating the address of control information in the lower control storage 9, and the like.

At this time, since the memory device is generally slower than the logical lower device, it takes a long time from the input of the address of the micro instruction to the address register 2 until the output of the micro instruction. Therefore, it is difficult for an information processing device having a short clock cycle to control the lower control memory 145 in one clock, and therefore it is necessary to hold it in the temporary address register 7. The control information in the lower control memory 9 is output in the next clock cycle.

Recent information processing apparatuses are required to have a high speed, and the clock cycle is becoming shorter. Therefore, it is necessary to speed up the circuit, but the signal transfer time between LSIs and the memory element are not so fast as compared with the logic circuit element, and these are factors that prevent the shortening of the clock cycle. There is.

Since the control information reading device shown in FIG. 8 uses two memory elements, the upper control memory 4 and the lower control memory 9, it is difficult to put them in one LSI. Further, since the lower control memory 9 needs to be arranged near a control target arithmetic unit or the like, the address of the lower control memory 9 often extends between two or more LSIs. Therefore, the clock cycle cannot be set to be equal to or less than the delay time between LSI + reading time of the memory, resulting in hindering the speedup.

In FIG. 8, 1 is a branch determination flag,
Reference numerals 3 respectively denote +1 adders. When it is not a branch instruction, the value of the address register is incremented by +1 to generate the next address, and when it is a branch instruction, the branch destination address of the micro instruction is stored in the address register 2. To be done.

The above-mentioned conventional control information reading device cannot shorten the clock cycle below the sum of the signal transmission time from the upper control storage device to the lower control storage device and the reading time of the lower control storage device, and This hinders the speedup of the entire processing device.

[0011]

OBJECT OF THE INVENTION It is an object of the present invention to provide a control information reading device which makes it possible to read control information from a control memory at a higher speed.

[0012]

A control information reading device according to the present invention stores N (N is 2 or more) which stores an upper control storage means and an address indicated by an address field among micro instructions sequentially read from the upper control storage means. (Integer) number of address registers, means for selectively activating the N number of address registers in order and storing the address in the activated address register, and corresponding to the N number of address registers. N is provided and the control information of the information processing apparatus is read by the storage address.
It is characterized by including a plurality of lower control storage means and a means for deriving the currently read information from the N lower control storage means.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The higher-order control memory 4 is a memory device that stores micro-instructions, and a field within the micro-instruction has a control information address field which is a read address of the lower-order control memories 9 and 10, and when a micro-instruction branches. The address of the branch destination of is included.

The address register 2 is a register that holds an address of a microinstruction and serves as a read address of the upper control memory 4.

The branch determination flag 1 is a flag indicating whether or not a micro instruction branches. If a branch is designated by the branch determination flag 1, the branch destination address in the microinstruction is stored in the address register 2, and if the branch is not taken, 1 is added to the value of the address register 2 by 1
The value of is stored.

The counter flag 5 is a flag whose state is inverted every other clock, and in this example, "0" and "1".
And shall be repeated alternately. The outputs of the flag 5 and the inverter 6 control the address registers 7 and 8 and the control information selector 11.

The address registers 7 and 8 are registers for holding the addresses of the lower control memories 9 and 10, respectively.
According to the contents of the counter flag 5, the value of the control information address field in the microinstruction read from the upper control memory 4 is set alternately.

The lower control memories 9 and 10 are storage devices in which the control information in the information processing device is stored, and output the control information of the addresses indicated by the address registers 7 and 8, respectively. The control information selector 11 is used for the lower control memories 9 and 10
Of the lower control memory 9 or 1 which is controlled by the counter flag 5 and which has been read.
Select 0 output.

Next, the operation of this information processing apparatus will be described with reference to FIG.
It will be explained using the time chart of. In the first clock cycle (1st T), when the address of the microinstruction (address 1) enters the address register 2, the microinstruction is output from the upper control memory 4. The microinstruction includes a field (control address 1) indicating the address of control information.

At this time, since the counter flag is 0, the address register 7 is strobed and the address register 8 is held. Therefore, the first T control address 1 is set in the address register 7. Since the address register 7 holds the control address 1 for 2T, the control information (control information 1) corresponding to the control address 1 is output from the lower control memory 9 during that period.

At the second T, the counter flag 5 is inverted to 1
Therefore, the control address 2 corresponding to the address 2 of the micro instruction is set in the address register 8. Since the address register 8 is held for 2T as in the case of the first T, the control address 2 is delayed by 1T from the lower control memory 9.
The control information 2 corresponding to is output.

In the third T, the control information 1 specified in the first T
Is about to be determined, the control information selector 11 selects the output of the lower control memory 9 and outputs the control information 1.

In the control information reading apparatus having such a structure, if the lower control memories 9 and 10 and the control information selector 11 are stored in one LSI, the clock cycle is determined by the upper control memory 4. Read time and LSI
Since the sum of the signal transmission time and the signal transmission time in the LSI is included, the time required for signal transmission between LSIs is not included, and the clock cycle can be shortened.

However, in such a configuration, it takes 2 steps from the determination of the address of the microinstruction to the output of the control information.
Since it takes T, it takes time to control. Therefore, the following configuration is conceivable for quick control.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. This embodiment differs from the above-mentioned embodiment in the following differences. That is, in FIG. 1, the same lower control storage 10 is provided in addition to the lower control storage 9. Then, the control information address field in the microinstruction is only set directly in the address registers 7 and 8, but a 1 adder 15 for predicting the next control information address by adding 1 to the control information address field is added to the address register 7, In 8, the control information address field and the output of the 1 adder 15 are switched and set.

In the next cycle, the control information selector 11
An address selector 12 is provided for selecting the address of the control information output from, that is, the address register 7 or 8 strobed in the next cycle.

The address selector 12 selects the value of the address register 8 according to the value of the counter flag 5 when the strobe of the address register 7 is instructed,
When the strobe of the address register 8 is instructed, the value of the address register 7 is selected. The address selector 12 indicates the control information address which is scheduled to be output in the next cycle.

A comparator 13 for comparing the value of the address selector 12 with the control information address field in the microinstruction is also provided. If the two match, the control information designated by the control information address field in the microinstruction is output in the next cycle, so the control information is output in the next cycle in which the address of the microinstruction is determined. It will be.

At this time, the address register 7 or 8 instructed to strobe by the counter flag 5
The output of the 1 adder 15 is set as the predicted address of the next control information address.

If the control information address field in the microinstruction and the value of the address selector 12 are different,
Since the control information output in the next cycle is incorrect, in order to invalidate the output of the control information selector 11 in the next cycle, the hold flag 14 for receiving 1T of the output of the comparator 13 is provided. Holds the circuit in the information processing device controlled by the control information selector 11.

Further, the control information address field in the microinstruction is selectively set in the address register 7 or 8 which is instructed to strobe by the counter flag 5, and the reading of the control information in the current microinstruction is started.
Since it takes 2T to read the control information, the comparator 13 holds the address register 2 in order to suppress the update of the micro instruction.

Next, the operation of the embodiment of FIG. 2 will be described with reference to the time chart of FIG. When the address (address 1) of the microinstruction is input to the address register 2 at the first T, the microinstruction corresponding to it is output from the upper control memory 4. The micro-instruction includes the addresses of the lower control memories 9 and 10 (control address 1).

At this time, since the counter flag 5 is "0", the address selector 12 selects the address register 8, but the address register 8 is undefined, which is different from the control address 1. Therefore, the comparator 13 becomes "1",
The control information output in the next cycle informs that it is incorrect.

When the comparator 13 becomes "1", the address register 2 is held and the control address 1 is set in the address register 7 as it is. Further, the hold flag 14 that receives the output of the comparator 13 is also set.

In the second T, since the counter flag 5 is "1", the control information selector 11 selects the output of the lower control memory 10. However, since the hold flag 14 is "1", the output is invalid. The address selector 12 selects the address register 7, and the control address 1 is stored in the address register 7 at this time.

Since the address register 2 is held at the first T, it holds the same address 1 as that of the first T. Therefore, the lower control storage address output from the upper control storage 4 remains the control address 1. Is becoming

Therefore, since the control address 1 in the microinstruction and the contents of the address selector 12 match and the comparator 13 becomes "0", the hold of the address register 2 is released and the hold flag 14 is also reset. ..

Since the counter flag 25 becomes "1", the address register 8 is set to the 1 adder 15, that is, the value obtained by adding 1 to the control address 1.

In the 3rd T, the control information corresponding to the control address 1 is output from the lower control memory 9, selected by the control information selector 11 and output.

FIG. 12 shows an example of the micro instruction in the embodiment of FIG. If the control information addresses are continuous, such as addresses A to A + 3, the control information is output in the next cycle after the microinstruction address is determined, so that control is performed 1T earlier than in the embodiment of FIG. Can be done.

In the embodiment of FIG. 2, the current control address plus 1 is used for predicting the next control address, but when the control addresses are not continuous due to branching of microinstruction or the like. , The prediction is wrong. Therefore, in a microinstruction with many branches and the like, a hold signal is frequently generated, so that the speed of the entire information processing apparatus decreases. Therefore, in order to make the prediction more reliable, the following configuration can be considered.

FIG. 3 is a block diagram showing the structure thereof.
In the present embodiment, instead of the 1 adder 15 in the embodiment of FIG. 2, an adder 16 for adding the next lower control storage relative address field in the micro instruction to the current lower control information address field in the micro instruction is used. To use.

FIG. 13 shows an example of the micro instruction in the embodiment of FIG. With this configuration, the next control address is specified in the microinstruction, so the prediction becomes more reliable, and even if the control address is not continuous or even if the microinstruction branches, it can be predicted. Can be suppressed.

In the embodiment of FIG. 3, the next lower control memory relative address field is added to the current lower control memory address field in the micro instruction to make the next control information address. If there are few, the next control information address cannot be indicated by a relative address if it is very far from the current control information address. The following configurations are conceivable to improve this.

FIG. 4 is a block diagram showing this structure.
In the present embodiment, the value of the next lower control storage address field in the microinstruction is used instead of the adder 16 in the embodiment of FIG.

FIG. 14 shows an example of the micro instruction in the embodiment of FIG. With this configuration, it is not necessary to provide an adder as in FIGS. 2 and 3, and since the next control information address is designated by the microinstruction, the next control information address can be accurately predicted even at the branch of the microinstruction. It will be possible.

In the embodiment of FIG. 4, since the next control information address is designated in the microinstruction, the next address can be predicted if it is a simple branch instruction. However, in the case of a conditional branch instruction that decides whether or not to branch depending on the result of the operation of the information processing device, there is a high possibility that the prediction will go wrong,
This leads to a decrease in the speed of the information processing device. The following configurations are conceivable to improve this.

FIG. 5 is a block diagram showing the structure thereof.
In the present embodiment, in order to predict the next control information address in the case of not branching, a 1 adder 15 for adding 1 to the current lower control storage address field in the microinstruction is provided.

In accordance with the branch determination flag 1, if the micro instruction branches, the conditional branch destination lower control storage address field in the micro instruction is selected, and if not branched, the next address selector 17 that selects the value of the 1 adder 15 is selected. Equipped with. This next address selector 17 is used instead of the 1 adder 15 of FIG.

FIG. 15 shows an example of the micro instruction in the embodiment of FIG. With this configuration, if the values of the current lower control storage address field in the microinstruction when not branching are continuous, it is possible to predict when not branching,
When branching, the next control information address can be specified by a microinstruction, so that prediction can be performed even when a conditional branch occurs.

In the case of FIG. 15, if the value of the current control storage address field in the microinstruction when the branch is not executed by the conditional branch instruction, the prediction will be missed if it is not continuous. Since a general information processing device tries to reduce the capacity of the lower control memory by designating the same control information with different micro instructions, the value of the current control memory address field is not always continuous. To enable prediction even if the values in the current control storage address field are not continuous, the following configuration is possible.

FIG. 6 is a block diagram showing the configuration of the embodiment. In this embodiment, instead of the 1 adder 15 of the embodiment of FIG. 5, the value of the current lower control storage address field in the microinstruction is the same. Adder 1 that adds the value of the relative address field of the uncontrolled branch destination lower control memory in the microinstruction
Equipped with 6.

FIG. 16 shows an example of the micro instruction in the embodiment of FIG. Almost the same as the embodiment of FIG. 5, but
In the case of a conditional branch instruction, the next control information address in the case of not branching can be specified by a micro instruction, so that the degree of freedom is increased compared to the case of FIG. 5 and the same control information can be specified by a plurality of micro instructions. There is an advantage that the capacity of the control memory can be reduced.

In the embodiment of FIG. 6, when a conditional branch instruction is issued,
Since the relative address is used to predict the next control information address in the case of not branching, the prediction cannot be performed if the current control information address and the next control information address are very far apart. In order to improve this, the following configuration can be considered.

FIG. 7 is a block diagram showing the configuration of the first embodiment, and FIG. 17 shows an example of the microinstruction in this embodiment. In this embodiment, the micro instruction has a current lower control storage address field, a non-conditional branch destination lower control storage address field, and a conditional branch destination lower control storage address field. Instead of the adder 16 of the embodiment of FIG. Use the value of the unconditional branch lower control store address field in the microinstruction.

With this configuration, the control information address can be specified in the microinstruction in the conditional branch instruction regardless of whether the branch is performed or not, so that the prediction is not lost and the speed of the entire information processing apparatus can be increased. Become.

In the above embodiment, the lower control storages 9, 1
Although 0 is set to 2, it can be set to 3 or more in general,
In response to this, the state of the counter flag 5, the registers 7, 8
It is clear that it is sufficient to increase the number and so on.

[0059]

As described above, according to the present invention, a plurality of lower control storage devices are provided and read from each lower control storage device in several clock cycles. By reading these in sequence, Since the control information is continuously and successively obtained as a whole, the clock cycle can be shortened and the speed of the entire information processing apparatus can be increased.

Further, by predicting the address of the next lower control storage device, the control information can be read in the next cycle in which the microinstruction is fixed, so that the control can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing still another embodiment of the present invention.

FIG. 5 is a block diagram showing still another embodiment of the present invention.

FIG. 6 is a block diagram showing still another embodiment of the present invention.

FIG. 7 is a block diagram showing another embodiment of the present invention.

FIG. 8 is a block diagram of a conventional control information reading device.

9 is a time chart showing the operation of the block of FIG. 1. FIG.

FIG. 10 is a time chart showing the operation of the blocks of FIG.

FIG. 11 is a time chart showing the operation of the conventional device.

FIG. 12 is a diagram showing an example of microinstructions used in the blocks of FIG.

13 is a diagram showing an example of microinstructions used in the blocks of FIG.

FIG. 14 is a diagram showing an example of microinstructions used in the blocks of FIG.

15 is a diagram showing an example of microinstructions used in the blocks of FIG.

16 is a diagram showing an example of microinstructions used in the block of FIG. 6;

17 is a diagram showing an example of microinstructions used in the blocks of FIG. 7. FIG.

[Explanation of symbols]

 1 Branch judgment flag 2, 7, 8 Address register 3, 15 1 Adder 4 Upper control memory 5 Counter flag 9, 10 Lower control memory 11, 12, 17 Selector 13 Comparator 14 Hold flag 16 Adder

Claims (7)

[Claims] 1. A high-order control storage means, N (N is an integer of 2 or more) address registers for storing an address indicated by an address field among micro-instructions sequentially read from the high-order control storage means, and Means for selectively activating the N address registers in order and storing the addresses in the activated address registers, and an information processing device provided corresponding to the N address registers Control information reading device including N pieces of lower control storage means for reading the control information of 1. and means for deriving the information currently read out of the N pieces of lower control storage means. 2. A high-order control storage means, means for predicting an address of a next cycle by adding a predetermined constant to an address indicated by an address field among micro-instructions sequentially read from the high-order control storage means, An address selecting means for selecting an address and an address for the next cycle, two address registers for storing the selected address of the address selecting means, and the two address registers are activated alternately in order. Means for storing and controlling the selected address of the address selecting means in the activated address register, and two means for providing control information of the information processing device by the stored addresses provided corresponding to the two address registers. Derivation of information currently read out from the lower control storage means and the two lower control storage means Comparing the address with the address of the address register in the inactive state of the two address registers, and if they are the same, the address selecting means is caused to select the next address, which is different. And a control means for controlling the address to be selected. 3. The upper control storage means and the relative address indicated by the next control information relative address field in the microinstruction is added to the address indicated by the address field of the microinstructions sequentially read from the upper control storage means. Means for predicting the address of the next cycle, address selecting means for selecting the address and the address for the next cycle, two address registers for storing the selected address of the address selecting means, and Means for selectively activating one of the address registers in turn and storing the selected address of the address selecting means in the activated address register,
Two lower control storage means provided corresponding to the two address registers to read the control information of the information processing device by the storage address, and the lower control storage means currently read out of the two lower control storage means. Derivation means for deriving information is compared with the address and the address of the address register in the inactive state of the two address registers, and if they are the same, the next address is selected by the address selection means. And a control means for controlling the address to be selected if different. 4. An upper control storage means, an address indicated by an address field of micro instructions sequentially read from the upper control storage means, and a next address indicated by a next control information address field in the micro instruction. Address selection means for selecting, two address registers for storing the selection addresses of the address selection means, and the two address registers are selectively activated in order, and the address selection is performed to the activated address register. Means for storing and controlling the selected address of the means, two lower control storage means provided corresponding to the two address registers and for reading the control information of the information processing device at the stored addresses, and the two lower control memories. Derivation means for deriving the information currently read out from the lower control storage means; Address and the address of the address register in the inactive state of the two address registers are compared, and if they are the same, the next address is selected by the address selecting means, and if they are different, the address is selected. And a control information reading device. 5. The upper control storage means and a cycle next to a cycle when the micro instruction does not branch by adding a predetermined constant to an address indicated by an address field among the micro instructions sequentially read from the upper control storage means. Means for predicting an address, and address prediction selecting means for selecting the address when not branching and selecting the address indicated by the branch destination address field in the microinstruction when branching according to the branch condition of the microinstruction. , Address selecting means for selecting the address and the output of the address prediction selecting means, and two address registers for storing the selected address of the address selecting means,
Means for controlling the storage of the selected address of the address selecting means in the activated address register by selectively activating the two address registers in turn, and the means provided corresponding to the two address registers. Two lower control storage means for reading the control information of the information processing apparatus by the storage address, a derivation means for deriving the currently read information from the two lower control storage means, the address and the two. The address of the address register in the inactive state among the address registers is compared with each other, and if the addresses are the same, the output of the address prediction selecting means is selected by the address selecting means, and if they are different, the address is selected. And a control information reading device. 6. The upper control storage means and the relative address shown in the next control information relative address field in the micro instruction to the address shown in the address field of the micro instructions sequentially read from the upper control storage means. Means for predicting the address of the next cycle when the microinstruction does not branch by adding, and the address of the next cycle if the branch does not branch, or the address of the next cycle if the branch does not branch, according to the branch condition of the microinstruction. Address prediction selection means for selecting the address indicated by the branch destination control information address field in the microinstruction, address selection means for selecting the address and output of the address prediction selection means, and selection address of the address selection means For storing two address registers and the two address registers Means for controlling the storage of the selected address of the address selection means in the activated address register by selectively activating the address registers alternately and information provided by the storage addresses provided corresponding to the two address registers Two lower control storage means for reading the control information of the processing device, a derivation means for deriving the currently read information out of the two lower control storage means, the address and the two address registers The address of the address register in the inactive state among them, and means for controlling the address selecting means to select the next address if they are the same, and to select the address if they are different. A control information reading device characterized by the above. 7. A high-order control storage means, an address indicated by an address field among micro-instructions sequentially read from the high-order control storage means, and a branch destination control of micro-instructions read sequentially from the high-order control storage means. Address selection means for selecting an address indicated by the information address field, two address registers for storing the selection address of the address selection means, and the two address registers are sequentially made active alternatively and active. Means for controlling the storage of the selected address of the address selection means in the address register, and two lower layers for the control information of the information processing device, which are provided corresponding to the two address registers and read the stored information. The control storage means and the currently read out of the two lower control storage means Derivation means for deriving information and the address and the address of the inactive address register of the two address registers are compared, and if they are the same, the branch destination control information address is sent to the address selection means. A control information reading device, comprising means for selecting an address indicated by a field, and controlling so as to select the address if different.