JPS63223852A - Information processor - Google Patents

Abstract

PURPOSE:To cut the number of address lines down to just a single piece and therefore to decrease the number of connectors, by outputting alternatively both 1st and 2nd addresses produced simultaneously from a CPU in time division by a multiplexer and supplying these addresses to a decoder of each I/O device. CONSTITUTION:A CPU 101 activates a control signal 104 with a fixed delay time after higher (1st) and lower (2nd) addresses are effective. A timing generating part 107 keeps the switch signal 108 of a multiplexer 105 at the higher address side while the signal 104 is active. When a 1st strobe 109 is first active when the signal 104 becomes active and the signal 108 is switched to the lower address side. Then a 2nd strobe 110 is set active after a fixed time. An I/O selection signal 114 becomes active with a delay equal to the delay of the decoding time after the strobe 109 is active.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device that selects an input/output device by decoding an address, and particularly to an information processing device that selects a specific input/output device by decoding an upper address, and selects a specific input/output device by decoding an upper address. The present invention relates to an information processing device that selects a specific internal register in a specific input/output device by decoding an address.

Conventionally, a part of the address space of the CPU (central processing unit) is allocated to the internal registers of the Ilo (input/output) device.
I-So-called memory ◆ Matsubuto Ilo (Memory
The Mapped Ilo method is commonly used. In this memory Matsubuto I10 system, memory space is usually allocated to the lower address of the address space, I10100 is allocated to the upper address, and each 110 device in the I10100 is allocated to a different address in more detail.

Additionally, the lower bits of the address are often used for the internal registers of each 110 device. For example, four 1-byte wide internal registers are selected by the lower two bits of the address.

FIG. 3 is a block diagram showing a conventional example of such an information processing device. In the figure, a central processing unit (CPU) 3
01 outputs an upper address 302 and a lower address 303 simultaneously in parallel when accessing a memory or an I10 device, and starts a bus cycle by a control signal 304.

The upper address 302 is input to the first decoder 305,
This decoder 305 detects that the address 302 is a specific I1.
If the address corresponds to the 0 device 306, the select signal 307 is activated. The lower address 303 is the second
A control signal 304 is input to a decoder 308 which activates an enable signal 309 for a particular internal register of a particular I10 device 306 via a control signal 304 .

In such an information processing device, when it is necessary to interconnect the address lines for each of the 110 devices between multiple packages via connectors, the address line from the CP Ll 301 is connected to the upper address line 302 and the lower address line 303. Since it consists of two lines, there is a disadvantage that the number of connector terminals increases.

OBJECT OF THE INVENTION Therefore, the present invention has been made to eliminate the drawbacks of the conventional devices, and its purpose is to provide an information processing device that can reduce the number of connector terminals. There is a particular thing.

According to the present invention, there is provided a central processing unit that generates first and second addresses temporally in parallel; An information processing device comprising: a first decoder that selects a device; and a second decoder that selects a specific internal register in the specific input/output device according to the second address; The present invention is characterized in that it has a multiplexer that inputs addresses No. 1 and No. 1 and a second address and selectively derives both addresses by time division, and supplies the output of the multiplexer to the first and second decoders. An information processing device is obtained.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Central processing unit! (CPU) 101 is memory or ■10
When accessing the device, the upper address 102 and lower address 103 are output simultaneously in parallel, and the control signal 1
04 starts the bus cycle.

In this embodiment, the bit width of the upper address and the lower address are each 16 bits.

A multiplexer (MtJX) 105 receives the upper and lower addresses 102 and 103 as input, and outputs the timing generator 1.
address line 1 by switching signal 108 from 07.
Either the upper or lower address 102 or 103 is alternatively output to 06. The output 106 of this multiplexer 105 is 16 bits.

The timing generation unit 107 generates a switching signal 108 . First strobe signal 109. The second strobe signals 110 are respectively controlled.

A latch circuit (L) 111 is connected to the address line 106 and latches the upper address using the first strobe signal 109. The upper address latched by the latch circuit 111 is input to the first decoder 112, and this first decoder 112 determines whether the address is a specific I10
If the address corresponds to device 113, select signal 1
Activate 14. A second decoder 115 is also connected to the address line 106 and decodes the lower address using the second strobe signal 110 to
0 Enable signal for a specific internal register of device 113 1
Activate 16.

FIG. 2 shows a timing chart of each signal in the block diagram shown in FIG. After the upper address and lower address become valid, the CPU 101 activates the control signal 104 with a certain delay time. The timing generator 107 keeps the switching signal 108 of the multiplexer 105 on the upper address side while the control signal 104 is inactive, and when the control signal 104 becomes active, first activates the second strobe 109. Next, the switching signal 108 is switched to the lower address side, and the second straw 1110 is activated after a certain period of time.

After the first straw 1109 becomes active, the I10 select signal 114 becomes active with a delay corresponding to the decoding time delay. After the second strobe 110 becomes active, the register select signal 116 becomes active with a delay corresponding to the decoding time delay.

In this way, the multiplexer and timing control unit output the addresses output from the CPU in a time-division manner, first outputting the upper address, then outputting the lower address, and then outputting the first address.
The strobe signal and the second strobe signal are activated when the upper address and lower address become valid respectively, and on the I10 device side, the upper address is latched by the first strobe signal and a specific Ilo is set by the second decoder. A second decoder is provided for selecting a specific internal register of a specific I10 device by means of a second strobe signal.

As a result, when interconnecting address lines for each of the 110 devices between a plurality of packages via connectors, the number of connector terminals can be reduced compared to the conventional method.

Also, by partially overlapping the time for decoding the upper address by the first decoder and the time for transferring the lower address on the address line,
This makes it possible to minimize performance degradation caused by multiplexing addresses.

Effects of the Invention As described above, according to the present invention, the first address (e.g., upper address) and the second address (e.g., lower address) that are simultaneously generated by the CPU are selected in a time-sharing manner by a multiplexer. Since the signal is outputted all at once and supplied to the decoders of each of the 110 devices, the number of address lines is reduced to one, which has the effect of reducing the number of connector terminals when connecting the connector.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart of signals of each part showing the operation of the blocks in FIG. 1, and FIG. 3 is a block diagram of an information processing apparatus illustrating a conventional system. Explanation of symbols of main parts 101... CPU 102... Upper address 103... Lower address 105... Multiplexer 112... First Decoder 113...I10 device

Claims (1)

[Claims] a central processing unit that generates first and second addresses in parallel in time; a first decoder that selects a specific input/output device from a plurality of input/output devices according to the first address; and a second decoder that selects a specific internal register in the specific input/output device according to the second address, the information processing device receiving the first and second addresses as input. 1. An information processing apparatus, comprising a multiplexer for selectively deriving both addresses by time division, and an output of the multiplexer is supplied to the first and second decoders.