JPH06332840A - Main memory control system - Google Patents

Abstract

PURPOSE:To reduce a signal line number from a main memory controller and to reduce components other than a main memory unit. CONSTITUTION:A timing generation circuit 5 and a selector 4 for receiving signals from the circuit and time-dividing and multiplexing module addresses and storage addresses are provided in the main memory controller 1. A latch 6 for inputting the multiplexed address, extracting the module address from the multiplexed address by the signal from the timing generation circuit 5 and latching it is provided in the main memory unit 9. The main memory unit inputs the multiplexed address and the module address from the latch 6, extracts the storage address from the multiplexed address by the signal from the timing generation circuit 5 and performs memory access by the extracted storage address and the module address from the latch.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory control system,
In particular, it relates to a main memory control system of a main memory device composed of a plurality of memory modules.

[0002]

2. Description of the Related Art In the prior art, as described in Japanese Patent Laid-Open No. 61-97759, when a memory area of a single memory module is expanded, the address to be expanded is preset. The number of signals on the address bus is reduced by latching and outputting the output of the latch to the address bus only when accessing the extended area. Further, when controlling the main memory composed of a plurality of memory modules, the addresses in the module (stream
Memory) and the address (module address) for selecting a required memory module.

[0003]

According to the above-mentioned prior art, in a storage system for controlling a main memory composed of a plurality of memory modules, the main memory control device has a storage address and a module address. And a large number of address signals for the main memory control device are required. Further, in Japanese Patent Application Laid-Open No. 61-97759, in addition to a latch circuit for latching an extended address, a comparison circuit for detecting whether the extended address is accessed or the like is required, and many constituent elements are provided outside the main memory device. It had the drawback of needing it. An object of the present invention is to reduce the number of signals from the main memory control device and reduce the number of components other than the main memory device.

[0004]

The present invention is applied to a main memory control system for controlling a main memory composed of a plurality of memory modules, and the main memory controller is provided with a timing generator. A circuit and a selector for receiving a signal from the circuit to multiplex the time division of the module address and the storage address are provided, and the multiplexed address is input to the main memory to generate the timing. A latch circuit for extracting and latching a module address from a multiplexed address by a signal from the circuit is provided, and the main memory device inputs the multiplexed address and the module address from the latch, and the timing generation circuit The storage address is extracted from the multiplexed address by the signal from Storage address and module from latch - so that memory accesses by address.

[0005]

According to the present invention, since the module address and the storage address are output to the address bus as the same signal, the number of signal pins of the main memory controller can be reduced. Further, the hardware such as the comparison circuit is not required, and the configuration can be simplified.

[0006]

EXAMPLE An example of the present invention will be described below. Figure 1
It is a figure which shows the whole structure of one Example of this invention. Reference numeral 1 is a main memory control device. 2 is a module address register,
Reference numeral 3 is a storage address register, 4 is a selector, and 5 is a timing generation circuit, which is provided in the main memory controller 1.

Reference numeral 9 is a main memory. 6 is a latch, 7 is a module address decoder, and 8 is a memory module. A module address 101 is output from the module address register 2 and a storage address 102 is output from the storage address register 3 to the selector 4. Here, the module address 101 is an address for selecting a desired memory module from a plurality of memory modules, and the storage address 102 is an address in the memory module. The timing generation circuit 5 supplies the selector 4 with the select signal 103 and the latch 6 with the module address latch timing signal 104.
To output a memory control signal 106 to the memory module 8. FIG. 2 shows the timing of each of the above signals.

In this embodiment, when the memory module 8 is accessed, the module address 101 output from the module address register 2 and the storage address 102 output from the storage address register 3 are accessed.
Are time-divided by the selector 4 under the control of the select signal 103 output from the timing generation circuit 5, and are multiplexed in the order of the module address and the storage address as shown in FIG. It is output from the main storage control device 1 as 105. Multiplex address 1 output from main memory controller 1
05 is directly input to the memory module 8 and simultaneously to the latch 6. Further, the latch 6 extracts the module address 101 from the multiplex address 105 according to the module address latch timing signal 104 shown in FIG. Module address 101 latched by latch 6
Is decoded by the decoder 7 and supplied to the memory module 8 to select a desired memory module. Then, the storage address 102 is extracted from the multiplex address 105 supplied to the memory module 8 by the memory control signal 106 shown in FIG. As a result, the memory area designated by the extracted storage address in the selected memory module is accessed. The module address 101 is fixed before memory access by the module address latch timing signal 104, and the selection signal after decoding does not change while the desired memory module is being accessed. .

When the number of memory modules is increased and more module addresses are needed, the modules are
The main memory control device by dividing the address into n times and time-multiplexing it to the address bus, outputting n module address latch timing signals, and latching them by n stages of latch circuits on the main memory device. It is possible to minimize the increase in the number of signals of. As described above, the number of signals from the main memory controller can be reduced by time-division multiplexing the module address and the storage address from the main memory controller and outputting them to the main memory.

[0010]

According to the present invention, a plurality of memory modules are provided.
In a main memory control system having a main memory composed of modules, the module address is multiplexed with the storage address and can be output from the same signal pin, so that the number of signals from the main memory controller is reduced. You can

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a timing of each signal in the example.

[Explanation of symbols]

 1 Main Storage Controller 2 Module Address Register 3 Storage Address Register 4 Selector 5 Timing Generation Circuit 6 Latch 7 Decoder 8 Memory Module 9 Main Storage Device

Claims (1)

[Claims] 1. A main memory device comprising a plurality of memory modules and a main memory control device for controlling the main memory device, wherein a desired memory module is selected from the plurality of memory modules by a module address. In the main memory control system in which a memory is selected and an address in the selected memory module is designated by a storage address, the main memory control device is provided with a selector and a timing generation circuit, and the selector is the module address. And storage
The address and the select signal from the timing generation circuit to receive the module address and the storage signal.
A multiplex address to output a multiplex address, input the multiplex address to the main storage device, receive a module address latch timing signal from the timing generation circuit, and receive a multiplex address from the multiplex address. A latch for extracting and latching the address is provided, and the main memory device inputs the multiplex address and the module address from the latch, receives a memory control signal from the timing generation circuit, and stores the memory address from the multiplex address. -Extracting the storage address and extracting the storage address and the module from the latch-
A main memory control method characterized by memory access by address.