JPH0343830A - Block repeating circuit - Google Patents

Abstract

PURPOSE:To perform a sequence where M pieces of instructions are repeated by N times as a single block in a pipeline processing system by repeating both sets of the head address of a block held in a program counter when the value of this counter is equal to M. CONSTITUTION:The value of a program counter 24 is increased one by one every time an instruction for a pipeline process is carried out by one step. When the value of the counter 24 is equal to M, the address held in an address holding register 22 is set again to the counter 24. Then the repeating frequency is held in a sequence frequency register 23. When the repeating frequency is equal to N, the repeating process is stopped and the next process is carried out. Thus it is possible to perform a sequence where M pieces of instructions are repeated by N times as a single block in a pipeline processing system.

Description

[Detailed Description of the Invention] [Summary] Regarding the block repeat method when iterative processing is performed using the pipeline processing method, it is possible to perform a sequence in which M instructions are repeated N times as one block using the pipeline processing method. The purpose is to
When performing a sequence in which M instructions are repeated N times as one block using the vibrine method, the M register holding the value of M, the N register holding the value N, and the M instructions are When an instruction indicating a sequence to be repeated twice is received, an address holding register is provided to hold the address next to the address of the instruction, and the value of the address holding register is initially set in the program counter.
Two instruction registers that hold instructions read from are connected in series, and the value of the first stage instruction register is decoded by a look-ahead decoder to obtain the address of the internal RAM in advance.The instructions for pipeline processing are executed one step at a time. The value of the program counter is increased by 1 each time the program is executed, and when the value of the program counter and the value of the M register match, the address held in the address holding register is reset to the program counter, and The number of repetitions of the sequence is held in a sequence number register, and when the number of repetitions of the sequence reaches N, the repeat processing is stopped and the process proceeds to the next processing.

[Industrial Field of Application] The present invention relates to a block repeat circuit for performing repetitive processing using a bus spline processing method.

[Prior Art] In program sequence control of program control type signal processing LSIs (particularly processors), processing using a pipeline method is performed in order to speed up signal processing. FIG. 6 is a block diagram showing an example of the configuration of a conventional circuit. Initially, selector 1 uses select signal PC8
1 selects the 1 side. Therefore, selector 1 selects "1". The output of this selector 1 enters an adder 2 and is added to the feedback signal.

The output of adder 2 enters selector 3;
Similarly to selector 1, the 1 side is selected. Therefore, selector 3 selects the output of adder 2,
The output of adder 2 is entered into program counter 4.

The initial value of the program counter 4 is set to 0 upon power-on reset. The output of the program counter 4 is fed back to the adder 2.
It is manually input to one side of the computer, and is also stored in the instruction ROM 5 as an address. Then, in synchronization with the machine clock, the output of the program counter 4 is converted to 1 by the adder 2.
It is incremented one by one.

The instruction stored in the instruction ROM address accessed by the address is read and entered into a circuit in which two instruction registers 6 and 7 are connected in series. First of all,
The output of the instruction ROM 5 enters the first instruction register 6 (IRI). The output of IRI is sent to the second instruction register 7 (I
Enter R2). During this time, the output of the IRI enters the look-ahead decoder 8, where internal RAM addresses and the like are calculated in advance and output. Then, at the next timing I
The instruction entered into R2 is decoded by the decoder 9 and executed. For example, MOV A.

When executing an instruction such as B (move the contents of the B register to the A register), the values of the A and B registers are obtained in advance by the look-ahead decoder 8, and when the decoder 9 executes the MOV instruction, Since the addresses of the A and B registers are known, instructions can be executed quickly (vibration line operation).

Note that the selector 1゜3 is set to 0 by the select signal pcso.
When the side is selected, a case may be considered in which when the jump destination address is entered in IR2, this address is set in the program counter 4 and a jump instruction is executed.

[Problems to be Solved by the Invention] When executing a repeat instruction (repeat instruction) in such a circuit, the program counter 5, IRI, IR
2. Stop the pipeline configured by the look-ahead decoder 8 and decoder 9 the number of times you want to repeat it, have the IR2 hold the instructions to be repeatedly executed, and
The output of R2 is processed by being repeatedly decoded by the decoder 9. Therefore, with the conventional circuit, it is not possible to repeatedly execute an instruction block consisting of a plurality of instructions.

The present invention has been made in view of these problems, and it is possible to set up N instructions by using M instructions as one block.
An object of the present invention is to provide a block repeat circuit that can perform a sequence that is repeated several times using a pipeline processing method.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 5 are designated by the same reference numerals. The circuit shown in the figure is
Assume that the circuit performs a sequence in which M instructions are treated as one block and repeated N times in a pipelined manner. In the figure, 20 is an M register that takes in and holds the value of M from the output of IRI, and 21 is the same (I
The N register 22 that takes in the value of N from RI and holds it is an address holding register that holds the address next to the address of the instruction when an instruction indicating a sequence of repeating M instructions N times comes.

23 is a sequence number register that holds the number of repetitions indicating how many times M instructions are repeated;
It is connected to the register 21.

24 is a program counter, which is incremented by l in synchronization with the machine clock. The output of the program counter 24 is given as an address to the instruction ROM 5, and is also connected to an address holding register 22, so that the start address of the repeat instruction is given to the address holding register 22. And M register 20
A control signal is input from the sequence number register 21 to the address holding register 22. 25 is a selector that selects either “1°” or the output of the address holding register 22;

[Operation] The value of the program counter 23 is incremented by 1 each time the pipeline processing instructions are executed one step at a time, and when the value of the program counter 24 and the value of the M register 20 match, the value of the M register 20 is increased. Under control, the address held in the address holding register 22 is reset to the program counter 24, and the number of repetitions of the sequence is held in the sequence number register 23. When the number of repetitions of the sequence reaches N, the address holding register 22 is controlled by the sequence number register 23.
The address held in is discarded, repeat processing is stopped, and the next processing is started. By doing this, a sequence in which M instructions are repeated N times as one block is created using a pipeline processing method. There is. Assume that the program instructions are as shown in (b). The program counter (PC) value (address value) is updated to 01.02, 03 (these values indicate hexadecimal. The same applies hereinafter), and the instruction at address 03 is updated to RE.
Assume that the instruction is PM, N (repeat the following instructions with the number of instructions M as one block N times).

At this time, the address next to the repeat instruction at address 03, that is, 04
Address data '04° of the address is set in the address holding register 22. In the illustrated example, the number of instructions M is 6 from 04 to 09. These six instructions are repeated N times as one block. (a
) shows the repetition. That is, the sequence from 04 to 09 is repeated N times from M, 1 to M, N.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a tank bottom block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals. In the figure, 30 is a two-man power adder, one of which has "1".
”, the feedback signal from the program counter 24 is input to the other input.The output of the adder 30 is input to one input of the selector 25.The other input of the selector 25 is the feedback signal from the program counter 24. Holding register 22
It contains the output of the select signal pCSI, pC32
One of them is selected by .

For example, when PC81 is inserted, side 1 is selected,
The adder 30 output enters the program counter 24 and the PC
When 82 is input, the 2 side is selected and the output of the address holding register 22 is input to the program counter 24.

31 is an OR gate which receives the machine clock CK on one input and a repeat start signal (1 level) or repeat end signal (0 level) on the other input, and its output is input to the address holding register 22 as a control signal.

32 becomes “1” or “2” when receiving the repeat start signal.
" is initially set, and the M counter 33 counts the number of instructions up to M from the set value. The M counter 33 receives the output of the N register 20 for one of the manual inputs, and the output of the M counter 32 for the other manual input, and compares the two. The comparator 33 generates the PC32 signal when the two match.

34 is an N down counter that sets the output of the N register 21 by a repeat start, receives a PC 32 signal and counts down every time the execution of the number M of instructions is completed, and generates a repeat end signal when the count reaches O. It is.

The down counter 34 corresponds to the sequence number register 23 in FIG. The operation of the circuit configured in this manner will be described below with reference to the timing chart shown in FIG.

In normal operation, the 1 side of the selector 25 is selected by the PC 81. Then, the new value of the program counter 24 is obtained by adding 1 to the value of the program counter 24 by the adder 30 using the machine clock CK as shown in FIG. 4(A). and,
The address holding register 22 is always set to the value of one cycle before by the machine clock CK, as shown in (c). Then, by using two instruction registers, IRI and IR2, the address of the internal RAM etc. is determined in advance by the look-ahead decoder 8 for the output of IRI, and is processed in parallel with the execution of the instruction in IR2. Line movement is taking place.

Now, write the repeat command REP to IRl as shown in (d).
When the instruction is entered, this instruction is decoded by the look-ahead decoder 8, and the repeat size is M.

N is required. The obtained values of M and N are stored in the N register 20. It is stored in the N register 21.

In other words, the N register 20 has M-6 as shown in (v).
is stored, and the repeat number N is stored in the N register 21.

When the repeat command REP enters IR2 in the next cycle,
It is decoded by a decoder 9. Then, by the repeat start signal decoded from the decoder 9, "2" is stored in the M counter 32 as shown in (G). This repeat start signal also enters the OR gate 31, and the machine clock C enters the address holding register 22.
Stop K's operation. When the operation of the machine clock CK is stopped, the address holding register 22 holds "04" as shown in (c). This "04" is the program counter value of the instruction following the repeat instruction REP.

At the same time, the M counter 32 starts counting.

Each time an instruction is executed, the value of the M counter 32 is updated by 1 as shown in (g).

The output of the program counter 24 is also 1 as shown in (b).
However, since the machine clock CK is stopped for the address holding register 22, its contents are (c).
There is no change as shown in . When the value of the M counter 32 matches the value (M-6) of the N register 20, the comparator 33 outputs a match signal PCS2.

This PC32C32 communication receiver 25 is entered, and only this time 2
side is selected, and the value held in the address holding register 22 (here, "04") is set in the program counter 24 again.

At the same time, this PC92 signal is sent to the N down counter 34.
, and cause its contents to count down by 1. Further, the M counter 32 is reset, and this time "1" is selected and starts counting from 1. In the next cycle, selector No. 3≠1 side is selected again, and the program counter 24 is incremented by 1 from the initial value "04".

Block repeat is performed by repeating the above operations. Then, when the value of the N down counter 34 becomes 0, it means that the repeat has been performed N times. Therefore, N
A repeat end signal "0" is output from the down counter 34, and the OR gate 31 is opened to allow the machine clock CK to enter the address holding register 22. As a result, the program exits the repeat cycle and executes the instruction starting from the next address.

FIG. 5 is a flowchart showing the operation of the present invention. The present invention provides an N register that holds a value of M, an N register that holds a value of N, and an instruction that indicates a sequence of repeating M instructions N times. An address holding register to be held is prepared (step 1), and the value of the address holding register is initially set in the program counter, and thereafter, two instruction registers for holding instructions read from the instruction ROM are connected in series. Each time a pipeline processing instruction, in which the address of the internal RAM is determined in advance by decoding the value of the first-stage instruction register, is executed step by step, the value of the program counter is increased by 1 (step 2). When the value matches the value of the N register, the address held in the address holding register is reset to the program counter, and the number of repetitions of the sequence is held (step 3). When the value becomes N, the repeat process is stopped and the process proceeds to the next process (step 4).

In the above-described embodiment, an N down counter for detecting the number of repeats N is used as the sequence number register, and a method of detecting when the value becomes 0 is used, but the present invention is not limited to this.

An N-up counter may be used to compare the output of the N-up counter with the value of the N register, and if they match, the repeat operation may be stopped.

[Effects of the Invention] As described in detail above, according to the present invention, the start address of a block to be repeated is held, the value of the program counter is incremented by 1 from this held address, and the value is set as the block address. number of instructions M
When the address of the block held in the program counter is reached, the start address of the block held in the program counter is set again for the required number of repeats N, thereby creating a pipeline that repeats M instructions N times as one block. This can be done using a processing method, which has great practical effects.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is an explanatory diagram of the operation of the present invention, Fig. 3 is a configuration block diagram showing an embodiment of the present invention, Fig. 4 is a timing chart showing the operation of each part, FIG. 5 is a flowchart showing the operation of the present invention, and FIG. 6 is a block diagram showing an example of the configuration of a conventional circuit. In FIG. 1, 5 is a program counter, 6.7 is an instruction register, 8 is a look-ahead decoder, 9 is a decoder, 20 is an N register, 21 is an N register, 22 is an address holding register, 23 is a sequence count holding register, 24 is a program counter.

Claims (1)

[Claims] M instructions are N as one block.
In the case where a sequence that is repeated several times is performed in a pipeline method, the M register (20) that holds the value of M, the N register (21) that holds the value of N, and the sequence that repeats M instructions N times are shown. When an instruction comes, an address holding register (22) is provided to hold the address next to the address of the instruction, and the value of the address holding register (22) is initially set in the program counter (24), and from then on. , command R
Two instruction registers (6) and (7) that hold the instructions read from OM (5) are connected in series,
The value of the first-stage instruction register (6) is decoded by the look-ahead decoder (8) and stored in the internal R in advance.
The value of the program counter (24) is incremented by 1 each time the pipeline processing instruction to obtain the address of AM is executed one step at a time, and the value of the program counter (24) and the M register (20) are
If the values match, the address holding register (22
) is reset in the program counter (24), and the number of repetitions of the sequence is stored in the sequence number register (23), and when the number of repetitions of the sequence reaches N, repeat processing is performed. A block repeat circuit characterized in that it is configured to stop and move on to the next process.