JPS6298427A - Associative type micro control system - Google Patents

Abstract

PURPOSE:To control dynamically a microprogram, and to decode and execute at a high speed an instruction word of an optional virtual computer by decoding an optional instruction word by an associative memory device, and branching it to the head address of the corresponding microprogram. CONSTITUTION:In order to execute freely a selection of an associated field, a mask register 2200 is provided against an instruction work 2100. An entry of an associative memory consists of an associative part 2012 and a pointer part 2015 for showing the head address of the corresponding microprogram 2310. As for the optional instruction work 2100, only a part corresponding to an operational code is effectuated by the mask register 2200, and decoded associatively in the associative memory 2000. When the decoded entry part is, for instance, 2030, it is made to branch to the head of the corresponding address 2330 of a microprogram 2300 by the contents of a pointer part 2035.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for controlling a microprogram in a microprogrammable data processing device.
In particular, a microcontrol method suitable for dynamically controlling microprograms [Background of the invention] Literature: Gin Iizuka, "Universal Host Processor"
, pp109-130, Kyoritsu Shuppan, [Dynamic
Architecture J, bit special issue 8゜1980,
In the conventional method for dynamically controlling microprograms described in 1999, the decoding operation of instruction words is sped up by the method shown in FIG. That is, a register 1100 for storing instruction words and a field selection circuit 12
00, and the start address 1300 of the corresponding microprogram previously stored in the high-speed memory IJ 1000 according to the selected offset value.
This is a method of branching to This method has the disadvantage that the field selection circuit 1200 is almost fixed and has little flexibility. In other words, even a branch table 1000 for undefined instructions must be prepared, and the high-speed memory 10
The degree of freedom is limited by the capacity of 00.

[Object of the present invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a microcontrol system that expands the instruction words of an arbitrary virtual machine into an optimal microprogram in a microprogrammable Φ data processing device, and efficiently realizes and executes the program.

[Summary of the invention]

In the present invention, an arbitrary instruction word is decoded by an associative memory device and branched to the corresponding microprogram start address. This eliminates the need for undefined instructions and undefined fields, and can be implemented using a small-capacity content addressable memory. For the part corresponding to the operand of the instruction word, an arbitrary bit string mapping conversion device is provided to convert it into a device-fixed bit string pattern, and a device-fixed control circuit is used to decode and execute it at high speed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 2 shows the method shown in FIG. 1 in an associative memory device 2500.
This was realized using. That is, the register 1100 in FIG. 1 that stores the instruction word is 2100 in FIG. 2, and the field selection circuit 1200 in FIG.
In FIG. 2, J 1000 is composed of an associative memory 2000. A mask register 2200 is provided for instruction M2100, which is a function not shown in FIG. 1, in order to freely select associated fields. Associative memory entry'
Reference numeral 2010 includes a pointer section 2015 indicating the start address of the microprogram 2310 corresponding to the association section 2012. For any 66-order candy 2100, only the portion corresponding to the opcode is validated by the mask register 2200 and associatively decoded in the associative memory 2000.

If the decoded IJ section is, for example, 2030, the program branches to the beginning of the corresponding address 2330 of the microprogram 2300 depending on the contents of the pointer section 2035.

FIG. 3 shows a circuit for hemasoping a pattern (register 3100) of a high-speed decoding circuit fixed in advance in the device in order to decode a portion corresponding to an operand of an instruction word 2100 at high speed. For example, the contents of bit 2110 of instruction word register 2100 are
115 and connecting part 3112 to A100 line 3115.
and stored in bit 3110 of register 3100.

The register 3200 stores values for determining the circuit pattern of the wiring circuit 3000. For example, bit 21
The connection position that determines the storage location of the contents of 10 is the register 32.
The contents of part 321o of 00 are determined by successively outputting from signal $3215.

FIG. 4 is a diagram showing the overall configuration of the present invention. Main memory 4
000, program counter 4100, main memo I
The contents of J 4000 are read out to instruction word register 210o via bus 4300. The mask register 2200 enables the part corresponding to the opcode, and the associative memo IJ
Decode by 2000. The address of the microprogram 2300 resulting from the association is stored in the microprogram counter 4600. The contents of the microprogram are read into register 3100. register 310
Some of the zeros are passed through bus 4500 to register 3200. Then, a bit string mapping conversion device 3000
is converted into a device-fixed bit string by , and the result is stored in a fixed location in register 3100 via bus 4400 . The microinstruction word stored in register 3100 is decoded by decoder 4200.

To explain the operation in I9, - First, an instruction is set in the instruction word register 2100. A microinstruction corresponding to the instruction is first read from the microprogram 2300. This microinstruction controls the bit string mapping conversion device in order to extract the operand part of the instruction word on the bus 4300 and set it in a predetermined position 1t of the register 3100.

Thereafter, microinstructions taken out from microprogram 2300 are decoded by decoder 4200 together with the operands set in this way.

[Effects of the Invention] According to the present invention, since the microprogram can be dynamically controlled, the command word of any virtual needle W machine can be decoded and executed at high speed. Furthermore, since the decoder is constructed using an associative memory, there is no need to provide an associative section for undefined portions, so there is no waste.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional method for decoding and executing an arbitrary instruction word, and FIG. 2 is a diagram showing a method for decoding and executing an arbitrary instruction word using an associative memory device. Figure 3 shows
FIG. 3 is a diagram showing a circuit that performs mapping conversion of an arbitrary bit pattern to another nobit pattern. FIG. 4 is a diagram showing the overall configuration of the present invention. 1000...high speed control memory, 1100, 2100...
...Instruction word storage register, 1200...Field selective 1 path, 1300.2300...Micro program section, 2000...Associative memory, 2200...Mask register, 3000...Bit pattern fist mapping Circuit, 2500...Associative memory device, 3100...
... Register, 3200 ... Mapping determination register, 4000 ... Main memory, 4100 ... Program counter, 4200 ... Microinstruction decoder, 46
00...Micro program counter.

Claims (1)

[Claims] 1. In a microprogrammable data processing device, an associative memory device for decoding arbitrary instruction words is provided,
An associative microcontrol system characterized by branching to the corresponding microprogram start address.