KR100337716B1 - A circuit forming the sum of products - Google Patents

Abstract

In processors, particularly digital signal processors, it is often necessary to form the sum of the products of concatenated data word pairs, for example in a correlation or convolution operation, one data word of each data word pair is +1. Or only one of the two values of -1. According to the invention, in this case, instead of forming a product in the multiplier, one data word of each pair of data words is provided to the addition / subtraction device to control functions relating to addition or subtraction, wherein one of the addition / subtraction units An input receives another data word of the data word pair and the other input is connected to the output of the accumulator register. Thus, a complex multiplier device is not used, and even if such a device is provided, it is not used to reduce the power loss of the processor.

Description

Circuit to form the sum of products

The present invention relates to a circuit for forming a sum of products of concatenated data word pairs, said circuit comprising: an addition / subtraction device having a function which can be switched in particular with respect to addition and subtraction by a first control input, said addition At least one accumulator register having an input that can be combined with an output of the addition / subtraction device and an output that can be combined with an input of the addition / subtraction device, and a control device that controls continuous multiplication processing.

Arithmetic operations of this kind are particularly implemented in digital signal processors, for example, implementing time-discrete correlation, filter and convolution operations as well as scala products. To help. A multiplier device is generally provided for successively receiving two data words of each pair of data words to execute the operation quickly, the output of the multiplier device being connected to one input of an add / subtract device, and the add / subtract The other input of the device is connected to the output of the multiplier device via a so-called accumulator register. If the device is properly configured, the necessary data word transfers as well as the multiply / accumulate steps can be executed within a single instruction cycle of the processor. The entire sum can then be formed even with multiple instruction periods equal to the sum of the data word pairs and some preliminary instructions.

Many fields of digital signal processing applications also include summing the products of concatenated data word pairs, where one data word of each data word pair can be regarded as one of +1 or -1 values. Examples of such applications include scal products, as well as time-discrete correlation, filters with binary bipolar coefficients and filter and convolution operations. Each time it is used, it is carried out in signal processing.

Forming such a sum using a multiplier device with a subsequent add / subtract device is used economically because the multiplier is only performed by the argument +1 or -1 in each other data word pair, That is, only the conditional change of the sign of these data words is realized.

U.S. Patent No. 4,849,922 describes a device of the kind mentioned above, which describes a device in which the multiplier is realized by arithmetically moving additions or subtractions. Although somewhat simpler than the configuration of a parallel multiplier device for an excited data word, the device is only economically used for multiplication by a factor of +1 or -1.

It is therefore an object of the present invention to provide a circuit of the kind mentioned above which is fast and simple in construction in this particular case of values for one data word.

The object is that in the processing of a data word pair in which one data word of each data word pair is provided with one of two bit values +1 or -1, the control device adds / subtracts individual values of the one data word. It is achieved in accordance with the present invention in succession of providing in parallel to at least one of the first inputs of the device, together with providing another data word of each data word pair to the other input of the addition / subtraction device.

Multiplication by a value of +1 or -1 during the calculation of the sum according to the invention corresponds to the corresponding control of the addition / subtraction device in which the other data word directly controls the function of the addition / subtraction device with respect to addition or subtraction. Replaced by. Thus, in each instruction period, a multiply-accumulate step is executed without using a multiplier device. However, even if the multiplier device is provided to process common data word pairs, power loss is generally less for special case data word processing because no signal conversion occurs in the multiplier device.

One data word value of each data word pair is provided directly to a control input while the other data word of the data word pair controls the add / subtract device so that it is necessarily provided simultaneously to the other input of the add / subtract device. . However, this always requires two transfer operations of the data words of each data word pair. To simplify this operation, the present invention provides a register for storing in parallel the values of one data word of at least a portion of a concatenated data word pair, the output of the register being a first control of the addition / subtraction device. Connected to at least one of the inputs, the register is a shift register comprising a plurality of stages in parallel, the stage output of one of the stages constitutes a register output, the register contents coming from the control device And a bit-wise shiftable by the first control signal. The register is thus output under the control of the control device which processes one data word of a plurality of consecutive pairs in parallel and controls these words in series, i.e. also supplying the other data word to the addition / subtraction device. . So each step requires only one data word transfer. Another embodiment in which the contents of the register can be moved in a selectable direction depending on the first control signal from the control device, and the register can be closed as an end-around coupled shift register. In addition, more general control over the processing of data words is possible.

If the output of the register is directly connected to the control input of the add / subtract device, the function of the device will in principle depend on the register contents, thus limiting the availability of the add / subtract device. Therefore, in another embodiment of the present invention, the function of the addition / subtraction device can only be controlled in accordance with at least one second control signal from the control device via a control input connected to the output of the register. This prevents the register from affecting the functionality of the add / subtract device. This can be achieved simply by connecting the output of the register to a control input of the add / subtract device via a logic circuit that receives a second control signal. As a result, an effective function can be achieved, and examples thereof will be described later in detail.

The circuit according to the invention can advantageously be used in a processor with at least one data bus, in particular in a digital signal processor. The stages of the register are then well coupled to the data bus, taking over data provided to the data bus under the control of a third control signal from the control device.

So transferring one data word to a register is performed by the control device in the same way as transferring another data word pair. The control device is then essentially well formed by the instruction decoder of the processor. Since the output of the register can be connected to the data bus and other registers of the processor can also be connected to the data bus in the same way, generally speaking the register may be used for storing any word during processing.

When the circuit arrangement according to the invention is used in a processor, the control device is a command decoder and preferably generates an active value of the first and second control signals only in response to the appearance of a predetermined command code. Due to this direct instruction-dependent control of the register and the add / subtract device, for example, two data words X, using a special instruction during an instruction clock period depending on the value of the first control signal, , You can perform arithmetic functions XY and X + Y on Y.

Embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram of a circuit according to the present invention.

2 is a diagram of an embodiment of a logical combination of register outputs.

1 shows a general block diagram of a processor, in particular part of a signal processor. The essential elements of the processor consist of an addition / subtraction device 10 consisting of so-called arithmetic and logic units, in which not only simple addition or subtraction of two data words is carried out but also other arithmetic with these data words. And a logic function is executed, which can be executed by a number of control inputs 9, except for addition and subtraction, which other functions are independent of the text content. The result of the processing function is in this case shown at the output Z connected to the plurality of accumulator registers 26a to 26n via connection 11, the result of which is shown under the control of the control signal on line 19. It can be transferred to one of the registers. The use of multiple registers is effective for many functions of the processor, but one register is sufficient for the functions described below.

Connection 11 and other connections and lines, as well as the connections leading to the inputs A and B shown by the stroke, are actually made up of a number of parallel lines, through which the data words are typically arranged in parallel. Is sent.

The contents of one of the registers 26a to 26n can be read by a control signal passing through line 21 and provided to input B of unit 10 via connection 27 and multiplier 18. Can be. As in multiplier 16, multiplier 18 is controlled by the control device via a control line (not shown for simplicity), which control device 19 and 21 are not described yet. Provide control lines. The control device essentially constitutes a command decoder which reads continuously from the command memory (not shown) and decodes the command words provided via the data bus 20a. The data bus 20a may also receive content read from one of the registers 26a through 26n.

Based on the control signal, the multiplier 18 connects either the output of the register 24 or the connection 27 to the input B of the unit 10. Similarly, the multiplier 16 connects the output of the connection 25 or register 22 from another element (not shown) of the processor to the input A of the unit 10 based on the control signal. . The registers 22 and 24, under the control of the control device 12 (not shown), each time a data word is provided by the memory 30, for example via a data bus 20, the data word. It is controlled to save. The data bus 20 may be identical to the data bus 20a, but may optionally use more than two data buses, and then connecting different data buses to the registers 22 and 24 may be used. It is possible.

So the device mentioned so far acts as an accumulator such that the connection 27 is connected to input B when the multiplier 18 is controlled. Each new data word provided to input A via the register 22 and multiplier 16 is then added to the contents of one of the registers 26a through 26n and stored well in that register again. Thus, the sum of a plurality of consecutively provided data words is formed.

If one data word of each data word pair can only have a +1 or -1 value, it is often necessary to form not only the sum of the concatenated data words but also the sum of the products of the concatenated data word pairs. Each of these data words is thus only one bit long, for example representing a coefficient. A register 14 is provided for the processing of the concatenated product, which register receives in parallel the bits of one data word of a concatenated pair of data words via, for example, a bus 20 and also controls the control device ( The data is recorded from 12 under the control of the control signal on the line 23. The register 14 is configured as a shift register comprising a plurality of stages, each stage storing one bit of a provided data word, by means of a control signal on the line 13 from the control device 12. Since the contents of all the stages can be moved in parallel, the contents of each stage appear in succession at the output 15 of the register 14. This output 15 is connected to the control input 9 of the addition / subtraction unit 10 via a device 28 which will be described later and the addition / subtraction unit 10 depends on the bit value appearing in the output 15. That is, it is switched to addition or subtraction according to one data word value of the data word pair.

The control signal on line 13 thus determines which data word of each data word pair is to appear at the output 15 of the register 14, and the memory 30 determines the data word of the data word pair. Control line 31 to read another data word associated with and provide the read data to input A of unit 10 via data bus 20 and register 22. Depending on the bit value on the output 15, the provided data word is added to or subtracted from the accumulated intermediate result thus far.

Looking at the actual timing, taking into account the transfer time and delay of the individual devices, first one bit value of one data word is transferred to the register 14 and then another data word of the data word pair is read from the memory and the register is read. And then the data word is processed by the register 22 to appear on output A after a short delay and at the same time register 14 receives a write preference so that one associated data word of the data word pair Appears on the output 15 and also on the control input 9 of the unit 10. However, the addition because the shift signal for the register 14 can be simply generated before writing a new data word into the register 22 or preferably simply after processing each other data word. The / subtraction unit 10 is already ready for the new function when another new data word appears at the input A.

When used in arithmetic operations other than the formation of sums of concatenation products, the function of the output / subtraction unit 10 by means of a signal on the output 15 of the register is disabled so that the output 15 A logic device 28 is connected between the control inputs 9 of the unit 10, which is controlled by the control device 12 via a control lead 17a. Thus, via the control lead 17a, the function of the unit 10 can be prevented from being affected by the signal on the output 15, in which case the function is a control line coming out of the control device 12. Exclusively controlled by the signal on (17).

Moreover, the outputs of all the stages of the register 14 are connected in parallel to the data bus 20a, the contents of all of the stages being controlled by the corresponding control signals from the control device 12. Can be sent to. Thus, the register 14 may be used as a temporary storage register when a special function for controlling the addition / subtraction device is temporarily not needed.

2 shows an example of the configuration of the logic device 28 and an example of the configuration of the addition / subtraction device 10, in which case only addition or subtraction can be executed substantially. Subtraction is performed with two's complement, that is, the addition of the lowest position addition unit as well as the complement of the value to be subtracted. For this purpose the addition / subtraction unit 10 comprises an adder 40, the inputs a, b of which are provided to the inputs A, B of the unit 10, the inverter stages 46 and 48 ), Or directly to the multipliers 42 and 44 in complementary form, and then the data words provided through the multipliers 42 and 44, respectively, are received. The adder 40 also includes a carry unit 41, the output Z of the adder 40 being connected to the connection 11.

The device can perform two functions, A-Bki or B-Aki, where ki is a coefficient with a value of +1 or -1 depending on the binary value shown in the output 15 of the register 14. For this purpose, two special commands are provided and in a first function, the control device of FIG. 1 generates a logic "1" on line i in control line 17a, which logic "1" is the device. Provided at the output of OR-gate 50 in (28), line 51 moves logic " 1 ", which multiplier processes the data word on input A without modification. The signal of the other input of the OR-gate 50 is irrelevant. When line j moves logic "O" and line 15 also moves logic "0" in line with k = -1, inverter 54 passes over OR-gate 52 on line 53. Generates a logic " 1 ", so that the data words on input B are also processed via the multiplier 44 without modification and the two data words are added without carry. However, if the line 15 moves logic " 1 " in accordance with k = + 1, the line 53 moves logic " 0 " so that the multiplier adds the complement of the data word on input B to the adder ( 40. The adder also receives an carry signal at carry input 41 so that AB appears at the output. In the second function, the line i shifts the logic "0" and the line j shifts the logic "1" so that if there is a logic "0" on the line 15, The sum of the two data words is formed again, whereas if there is a logic " 1 " on the line 15, a difference BA is formed on the output Z of the adder 40 corresponding to k = + 1. Thus, by the contents of the register appearing in the output 15, it is determined whether the addition / subtraction unit 10 forms the sum or difference of the two data words provided (the register is a cyclic shift register). Configured), the signals on lines i and j generated in accordance with the particular instruction determine the sign of the difference so that each of these arithmetic operations can be executed in only one instruction clock period.

When the two lines i several j move logic "0 ", by the other inputs (not shown) of the multipliers 42, 44 well controlled by the control device of FIG. It is possible to determine whether the subtraction unit 10 forms a sum or difference of the applied data words.

Thus, the device shown in FIG. 1 and detailed in FIG. 2 can simply form the sum of the product of multiple data word pairs when one data word of each data word pair only shows +1 and -1 values. One data word pair is processed every instruction period.

Claims (8)

A circuit for forming a sum of products of concatenated data word pairs, Means for supplying first and second data words of said data word pairs, said first data words represented by a sign value; An add having two data inputs, a first control input, a second control input, and an output and executing one of addition and subtraction in response to control signals received at the first control input and the second control input / Subtraction device; At least one accumulator register having an output coupled to an output of the add / subtract device, the output coupled to one of the two data inputs of the add / subtract device; Having a predetermined number of stages, parallel inputs, and a serial output coupled to the first control input of the addition / subtraction device, the sign values of the first data words of at least some of the concatenated data word pairs; A shift register for storing in parallel, wherein each sign value is bit-wise shifted by a shift control signal; And Coupled to the supply means and the shift register to control the parallel transfer of the first data words of at least some of the concatenated data word pairs to the parallel inputs of the shift register, the first data words A control device controlling writing to the stages of the shift register, the controlling device supplying shift control signals to the shift register to transfer the second data weeds to another data input of the add / subtract device; Circuit that forms the sum of products of concatenated data word pairs. The method of claim 1, Contents of the shift register can be shifted in a selectable direction based on other control signals from the control device; Wherein the shift register is closed as an end-around coup1ed shift register to form a sum of products of concatenated data word pairs. The method of claim 1, The function of the addition / subtraction device is supplied to the second control signal supplied from the control device 12 and received at the second control input of the addition / subtraction device via the control input connected to the output of the shift register. Circuit which in response is controlled to form a sum of products of concatenated data word pairs. The method of claim 3, wherein The output of the shift register forms a sum of products of concatenated data word pairs connected to the first control input of the add / subtract device through a logic circuit that receives the second control signal from the control device. Circuit. The method of claim 1, Used in the processor, including at least one data bus, The stages of the shift register are coupled to a data bus to form a sum of products of concatenated data word pairs that receive data provided to the data bus under control of a third control signal from the control device. The method of claim 5, The control device 12 is, as a command decoder, a sum of the products of concatenated data word pairs that generates an active value of the first and second control signals only in response to the appearance of a predetermined command code. To form a circuit. The method of claim 2, The function of the add / subtract device is controlled in response to control signals supplied from the control device via a control input connected to the output of the shift register and repaired at the second control input of the add / subtract device. Circuit for forming a sum of products of concatenated data word pairs. The method of claim 2, Used in the processor, including at least one data bus, The stages of the shift register are coupled to a data bus to form a sum of products of concatenated data word pairs that receive data provided to the data bus under control of a third control signal from the control device.