JPS62271017A - Addition and subtraction device for decimal number - Google Patents

Abstract

PURPOSE:To reduce the degree of dependence upon software and also to decrease the number of processing steps in order to increase the processing speed of an addition/subtraction device for decimal numbers, by providing a logic arithmetic circuit and using an operator calculated by said arithmetic circuit to perform the operation of absolute values of two numbers. CONSTITUTION:Two numbers are stored in registers 21 and 2$2d respectively and the codes of these numbers are supplied to a logic arithmetic circuit 1 from the digit positions accordant with these code types together with an operator showing the addition or subtraction via code selecting circuits 51 and 52 and code checking circuits 61 and 62. The circuit 1 performs a logic operation to obtain a desired operator from the codes showing the plus and minus of two numbers to undergo operations and said operator. While the absolute value excluding the code parts of those two numbers stored in registers 21 and 22 is sent to a decimal number arithmetic circuit 4. The circuit 4 performs an operation with the operator received from the circuit 1 under the control of an arithmetic indication means 3. If the number (a) obtained by the operation is negative, the obtained plus and minus codes are inverted to obtain a desired arithmetic result.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In order to perform addition and subtraction of decimal numbers, an operation is performed using a sign indicating the positive or negative of the two numbers to be added or subtracted and an operator indicating addition or subtraction. A logical operation circuit is provided to calculate an operator for execution, and the calculated operator is used to perform calculations based on the absolute values of the two numbers, thereby simplifying and speeding up the processing.

[Industrial application field]

The present invention relates to a decimal number addition/subtraction device applied to a processor system that performs decimal number addition/subtraction processing.

[Conventional technology]

As a conventional technique for adding and subtracting decimal numbers, there is known an arithmetic processing method in which the calculation of the formula shown in the fourth column of Table 1 below is replaced with the calculation of the equivalent formula in the fifth column.

The table above shows eight types of operations based on the combination of the sign of the number a in the first column, the + or - operator specifying addition or subtraction in the second column, and the sign of the number in the third column. The fourth column shows this using a mathematical formula.

When performing an operation according to the formula in the fourth column, for example, as is clear from the formula in the second column, it is not possible to perform an operation simply using the specified operator, and the sign of the two numbers to be operated cannot be calculated. It is necessary to perform calculations after identifying each. Therefore, in order to process this operation using a processor, there are two steps: identifying the signs of the two numbers to be operated on, and calculating the operator to actually process from these signs and the specified operator. Three steps are required: a step and an arithmetic processing step.

If we transform the formula in the fourth column into the formula shown in the fifth column, there is no need to consider the signs of the two numbers to be calculated, and it is sufficient to perform the calculation on the absolute values of each of these two numbers. However, the operator must be the operator shown on the left side of No. 6 JI1), so the 4 shown with an asterisk on the right side of the same column.
In addition, in the case of the four operations shown in the fifth row and below, that is, when the number a is negative, the sign of the obtained operation result must be reversed. Therefore, if the processing is performed by software, a significant reduction in the number of steps cannot be expected compared to the case where the calculations in the fourth column are directly executed.

Conventionally, when adding or subtracting decimal numbers, the above calculations were performed using software, which required a large number of processing steps or instruction steps, and therefore could not be done quickly in small-scale systems such as personal computers. It was difficult to carry out appropriate treatment.

[Problem that the invention seeks to solve]

The present invention achieves the following by providing a simple logic operation circuit.
This method aims to improve the processing speed of decimal addition and subtraction by reducing the dependence on software and reducing the number of processing steps.

Means for Solving Problem C] FIG. 1 is a block diagram showing the principle of the present invention, and shows the signs indicating the plus/minus of the numerical values a and b stored in the registers 21 and 22, and the operations indicating addition/subtraction. a logic operation circuit 1 that calculates an operator for executing specified addition/subtraction from the child, and the absolute values of two numbers to be calculated according to instructions from the operation instruction means 3 and the operator from the logic operation circuit. A decimal number arithmetic circuit 4 is provided which performs arithmetic operations.

Furthermore, as an embodiment of the present invention, a code selection circuit 5 is provided which selects and extracts a sign indicating the sign of a number to be operated in order to process numerical values having different code formats, A check circuit 6 for checking the accuracy can be added as desired.

In addition, an operator register 7 and a sign register 8 are provided so that when an interrupt occurs to the processor, the stored contents are saved in another storage means. store the operator,
The code register 8 can store the codes of two numbers to be operated.

[For production]

In the principle diagram shown in FIG. 1, two numbers to be added and subtracted are stored in registers 21 and 22, respectively, and the codes of these numbers are selected from the digit positions corresponding to the code format of the numbers by code selection circuits 51 and 52. It is supplied to the logic operation circuit 1 together with an operator indicating addition or subtraction via check circuits 61 and 62, and the logic operation circuit 1 operates on the two numbers to be operated as shown in the first to third columns of Table 1 above. 4. Signs indicating the positive/negative of and operators indicating addition/subtraction. Perform the □ logical operation to obtain the operators shown on the left side of column 6 of the same table.

Note that the code selection circuit 5 and the code check circuit 6 are not essential components of the present invention, but are provided as embodiments, and detailed explanations thereof will be given later.

On the other hand, the absolute values of the two numbers stored in the registers 21 and 22, excluding the sign part indicating the sign, are sent to the decimal arithmetic circuit 4, and are sent to the decimal arithmetic circuit 4 under the control of the arithmetic instruction means 3. Calculations are performed using operators from , and if the calculated number a is negative, the sign of the obtained result is reversed to obtain the desired calculation result. Note that if only the absolute value of the calculated result is required, it is clear that this sign inversion is not required.

According to the arithmetic device according to the present invention, the decimal number arithmetic circuit 4
The operation can be performed using the operator from the logic operation circuit 1 regardless of whether the two numbers are positive or negative, and addition and subtraction processing can be performed by one type of operation instruction to this decimal number operation circuit, so the processing speed is improved. It also makes programming easier.

As an embodiment of the present invention, in view of the fact that the digit positions of the positive and negative signs differ depending on the code format indicating the number, data in the digit positions indicating the positive and negative signs of numerical data stored in a register or the like is selected and retrieved. Sign selection circuits 51, 52 can be provided to select the positive and negative signs of the two numbers and supply them to the logical operation circuit l. In other words, the PACK format or Zone code format is used to represent numbers.
The format is known, and as shown in Figure 3, ±123
In the PACK format, the sign indicating the positive or negative of
In the ne format, they are placed in the upper digits of the least significant digit, and the principle diagram of FIG. 1 illustrates a case where a sign indicating the positive/negative is stored in the most significant digit or the least significant digit.

In another embodiment, a check circuit 61 checks for the presence of an error in the code read out as described above or the code read out directly from a predetermined digit position.
62 can be provided, which allows the positive sign (i
1) When there are numbers or symbols other than (usually A, C, E, F) and negative signs (usually B, D), an error signal should be sent from this check circuit. Can be done.

Further, as another embodiment, code registers 81 and 82 that store the codes of two numbers input to the logic operation circuit 1
In addition, the contents of this register are saved when the processor is interrupted. Furthermore, an operator register 7 is provided to store the operator output from the logic operation circuit 1, and the contents of this register are also saved to the processor. If there is an interrupt, it is saved (by this, even if the processor is interrupted in the middle of an operation, it is possible to complete the required operation without error).

〔Example〕

FIG. 2 shows an embodiment of the present invention, and components corresponding to those in the principle diagram of FIG. 1 are denoted by the same reference numerals.
゛Numeric registers 21 and 22 store numbers a and numbers respectively, and the positive and negative signs of these numbers are stored in the least significant digits, and the arithmetic register 1) stores this value. A + or - operator is stored that indicates the addition or subtraction of two numbers.

The code check circuits 61 and 62 are BC with each digit being 4 binary digits.
If D code is used, the value of the digit indicating the code is A-
If it is F, the sign is normal, so output “0”.
If it is 0 to 9, it is an error, so it outputs "l" indicating an error, and when at least one code check circuit detects an error, it sends out an error signal via the OR circuit 14.

The code check circuits 61 and 62 have the values of the digits indicating the above code A-F (“1010” to “1)1)” in hexadecimal notation.
), if the value is A, C, E, F, it will be ``0'' indicating a positive value, and if it is B, D, it will be ``1'' indicating a negative value. ” is output to the logical operation circuit 1.

If the number a and the number square are to be added, "O" indicating addition is output from the arithmetic register 1), and the first exclusive OR circuit (hereinafter referred to as EOR circuit) of the logical arithmetic circuit 1 is outputted from the arithmetic register 1). ) 12 is logically operated as "O" or "1" indicating the sign of the number a, but if the sign of a is positive, then "
O” is logically operated and “1” is output, and then the second E
“O” or “1” indicating the positive or negative of the number by the OR circuit 13
If the number is positive, "0" and "1" from the first EOR circuit 12 are used to output an "O" output that instructs addition to the decimal number calculation circuit 4. .

The following Table 2 is a logic value table of this logic operation circuit (however, it is shown in negative logic).

In the above table of Table 2, "0" in the +1) and (5) columns is addition, "l"
indicates subtraction, “0” in columns (2) and (4) is positive, “work”
indicates a negative value, and column (3) indicates the logic operation circuit l.
The column (5) is the output of the second EOR circuit 13 of the logic operation circuit 1, and the * in the column (5) indicates that the operator has been changed.

The decimal number calculation circuit 4 performs calculations between the numbers a from the registers 2i and 22 and the absolute value of the numbers using the operator from the logic calculation circuit l, and if the sign of the calculated number a is negative, this A desired calculation result can be obtained by inverting the sign of the calculation output. As mentioned earlier, A-F is used as the sign to indicate positive or negative, but generally speaking, inside a processor, if it is positive, it is represented as “C” (“1” in binary) 00
”), and if it is negative, it is “D゛ (“1)01” in binary system), so in this example, the least significant digit of the code is “0” and “1”. If it is reversed between, a positive or negative number is converted into a negative or positive number.

The operation instruction given to the decimal number operation circuit 4 to perform this operation may be the same instruction regardless of whether the numbers a and b are positive or negative.
Therefore, since there is no need to consider the signs of these numerical values in software, the burden on the programmer can be reduced.

〔Effect of the invention〕

In the present invention, by configuring the means for transforming a given arithmetic expression into an arithmetic expression suitable for execution using hardware, an arithmetic operation can be performed by one type and one arithmetic instruction regardless of whether the number to be operated on is positive or negative. Since the program is executed, not only the processing speed is significantly improved, but also the special effect of not having to consider the sign of the numerical value calculated during program creation can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of the invention, FIG. 2 is an embodiment of the invention, and FIG. 3 is an example of a code format for indicating numerical values. 1 is a logic operation circuit, 2 is a numerical value register, 3 is an operation instruction means, 4 is a decimal number operation circuit, 5 is a code selection circuit, 6 is a code check circuit, 7 is an operator register, and 8 is a code register.

Claims (5)

[Claims] (1) Logical operation circuit that selects an operator based on the signs of two numbers to be added and subtracted and an operator that specifies addition and subtraction (1)
and two numerical registers (2_1, 2_2) that respectively store the absolute values of the two numbers mentioned above, and an operation instruction means (3) that instructs execution of addition and subtraction of the absolute values of the two numbers stored in these registers. , comprising a decimal number calculation circuit (4) that performs calculations between the absolute values of the two numbers based on the operator selected by the logic calculation circuit and addition/subtraction execution instructions from the calculation instruction circuit. A decimal number addition/subtraction device. (2) Code selection circuit (5_1, 5_2) that selects the codes of two numbers to be added or subtracted according to the decimal code format.
2. The decimal number addition/subtraction device according to claim 1, further comprising: a decimal number adding/subtracting apparatus according to claim 1, wherein an output indicating a code from the code selection circuit is provided to the logic operation circuit. (3) A sign check circuit (6_1, 6_2) is provided to check for errors in the signs of two numbers to be added or subtracted, and the logic operation circuit performs a logical operation when there is no error in the signs. A decimal number addition/subtraction device according to claim 1 or 2. (4) Store the operator selected by the logic operation circuit,
A decimal number addition/subtraction device according to any one of claims 1 to 3, further comprising an operator register (7) whose contents are saved when the processor is interrupted. (5) Code registers (8_1, 8
_2) A decimal number addition/subtraction device according to any one of claims 1 to 4.