JPS62293432A - Information processor - Google Patents

Abstract

PURPOSE:To improve the performance of a microprogram, and to decrease micro-instruction words by providing a control storage device for executing an exception processing. CONSTITUTION:An exception detecting means 1 detects an arithmetic operation exception, etc., and applies plural exception detecting signals to an encoder 20. The encoder 20 encodes the exception detecting signal by taking a priority and applies an exception code as an address signal to a memory decoder 3 through an exception register 21. The memory address decoder 3 supplies an address circuit 50 with the head address of a series of microprograms for executing an exception processing corresponding to the exception code which is stored in a control storage device 52, and also, feeds attribute information of the exception code to an attribute display means 4. A control storage means 5 reads out a micro-instruction word, based on the fed head address, and outputs it as a control signal from a signal line 504 to an arithmetic unit through a control register 53.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device employing an exception interrupt method.

[Conventional technology]

Conventionally, when this type of information processing apparatus detects an exception, it loads a specific microprogram that handles the exception and handles the exception and interrupt.

[Problem that the invention seeks to solve]

In the conventional information processing apparatus described above, the microprogram determines the type of exception, which has the disadvantage of reducing performance and increasing the number of microinstructions.

[Means for solving problems]

The information processing device of the present invention includes an exception detection means for detecting exceptions such as memory access exceptions related to soft instruction words and operands to be processed and arithmetic exceptions generated by execution of instructions, and a plurality of exceptions detected by the exception detection means. encoding means for converting an exception detection signal into an exception code; and a start address of a series of microprograms given an address by the exception code generated by the encoding means and performing exception processing corresponding to the exception code and the exception thereof. a memory decoder that outputs attribute information of the exception indicated by the code; and an attribute display means that holds the attribute information and displays it on a microgram.

and control storage means for starting an exception interrupt processing operation in response to the start address of the microprogram output from the memory decoder.

〔Example〕

Next, nine aspects of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of the present invention. This information processing device includes an exception detection means 1,
It is composed of an encoding means 2, a memory decoder 3, an attribute display means 4, and a control storage means 5.

The exception detection means 1 is an exception detection circuit that detects an access exception to a memory (not shown) related to an instruction word or operand of a software instruction to be processed by the information processing apparatus, an operation exception generated by execution of an instruction, and the like. A plurality of exception signals eXo% eXi detected by the exception detection circuit are connected to the signal line 10.
0 to the encoding means 2.

Encoding means 2 includes an encoder 20 and an exception register 21
It consists of The encoder 20 receives the exception detection signal a
x, ~ex, are prioritized and coded, and the exception code eTl is sent to the exception register 2 via the signal line 200.
Output to 1. The exception code group held by the exception register 21 is given to the memory decoder 3 as an address signal via a signal line 201.

The memory decoder 3 has a capacity corresponding to the exception code EN, and the word corresponding to each EN contains the start address Ea of a series of microprograms that performs exception processing corresponding to the exception code EN, and attribute information At of the exception code EN. It consists of The start address Ea of a series of microprograms for performing the exception handling is given to the control storage means 5 via a signal line 301. The attribute information At is the signal line 3
00 to the attribute display means 4.

The attribute display means 4 is a register consisting of a plurality of bits, which holds the attribute information At, and outputs its contents via a signal line 400 to display it on the microprogram.

The control storage means 5 is composed of an address circuit 50, an address register 51, a control storage device 52, and a control register 53. The start address Ea of the series of microprograms that performs the exception handling is the address circuit 5 at the time of exception detection.
0 and is applied to the address register 51 via the signal line 500. Address register 51 is a register that holds microinstruction word address Ma. This microinstruction word address Ma is sent to the control storage device 52 via a signal line 501.
given to. The control storage device 52 is a memory that stores a plurality of microinstruction words, and outputs the microinstruction word corresponding to the microinstruction word address Ma via signal lines 502 and 503. The signal output via signal 1502 is the address Na of the microinstruction word to be executed next to the current microinstruction word.

Signal Cp output via signal line 503 is given to control register 53. A control signal Ce held by the control register 53 controls an arithmetic unit (not shown) via a signal line 504.

FIG. 2 shows the data format of the register which is the attribute display means 4. As shown in FIG. The interrupt code in the figure corresponds to the exception code EN notified to the software program, and attributes O to 3 display the attributes of the interrupt code (for example, inhibition type exception, completion type exception, etc.). be.

FIG. 3 is a truth table of the encoder in FIG. Third
In the figure, there are 16 input exception signals.

Let these signals be exceptions 0-15. The output signal en is expressed in 4 bits and its contents are as shown in the figure.

〔Effect of the invention〕

As explained above, the present invention converts the exception detected by the exception detection means into an exception code, and further inputs this exception code to the meso decoder to start a series of microprograms that performs exception processing corresponding to the exception code. Furthermore, the performance of a series of microprograms that performs two-interrupt processing can be improved by notifying the interrupt code to be notified to the software program corresponding to the exception code and the attribute information of the interrupt code using the attribute display means. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram 7 of an information processing apparatus showing an embodiment of the present invention. FIG. 2 shows an example of the data format of the attribute display register, which is the attribute display means 4 in FIG. 1. FIG. 3 is a truth diagram of an example of the encoder 20 of FIG. Explanation of symbols: lφ exception detection means, 2...encoding means, 3...
Memory decoder, 4... Attribute display means, 5... Control storage means, 20... Encoder, 21... Exception register. 50...Address circuit, 51...Address register. 52... Control storage device, 53... Control register, 1
00゜200.201,300,301,400,50
0~504...Signal line ° ゛. 7 ゛) Bedejin (7783) Patent Attorney Hiroyasu Ikeda 1, ,! Fan 1 diagram

Claims (1)

[Claims] 1. In an information processing device that operates in a microprogram system, an exception detection means for detecting exceptions such as memory access exceptions related to instruction words and operands of software instructions to be processed and arithmetic exceptions generated by instruction execution;
encoding means for converting a plurality of exception detection signals detected by the exception detection means into exception codes; and a series of encoding means for performing exception processing corresponding to the exception code, which is given an address by the exception code generated by the encoding means. a memory decoder that outputs attribute information of the exception indicated by the start address of the microprogram and its exception code; an attribute display means that retains the attribute information and displays it on the microprogram; An information processing device comprising: control storage means for starting an exceptional interrupt handling operation in response.