JPH0550015B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a microprogram-controlled information processing device using a virtual computer method, and particularly to an exception interrupt method. [Prior Art] Conventionally, this type of information processing device has reported a detected exception as a single exception code even when the device is operating as a virtual computer. [Problems to be Solved by the Invention] The conventional information processing device described above reports the detected exception as one exception code, so when the device is operating as a virtual computer, the detected exception is The drawback is that when it is necessary to report an exception code or format that is different from the state in which it is operating as a virtual machine, the exception code must be converted. [Means for Solving the Problems] The information processing device of the present invention has a VM mode flag indicating whether the device is operating as a virtual machine, and a VMID that holds a virtual machine identification number indicating the type of virtual computer. Exception detection means detects access exceptions to memory related to registers and instruction words and operands of instructions to be processed, and exceptions that occur due to instruction execution, and the exception detection signal detected by the exception detection means is assigned an exception number. a memory decoder that outputs an exception code whose address is given by the VM mode flag, VMID register, and exception number; and a memory decoder that stores and stores the exception code output from the memory decoder. It has an exception code register for displaying and a control memory in which a plurality of microinstruction words are stored, and control storage means for sequentially outputting microinstructions in response to an exception detection signal from the exception detection means. [Operation] By creating an exception code using the VM mode flag, VMID register, and exception number, you can change the architecture without being aware of whether the device is operating as a real computer or a virtual computer. Different exception codes can be created, eliminating the need for exception code conversion. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing essential parts of an embodiment of an information processing apparatus of the present invention. This information processing device has VM mode flag 1.
It has a VMID register 2, an exception detection means 3, an encoding means 4, a memory decoder 5, an exception code register 6, and a control storage means 7. VM mode flag 1 is a flip-flop indicating that the device is operating as a virtual machine.
When it is "0", it indicates that the device is operating in the real computer mode.When it is "1", it indicates that the device is operating in the virtual computer mode. Book
The value of VM mode flag 1 is output as signal VM. VMID register 2 is a register that holds a virtual machine identification number indicating the type of virtual machine that is operating when the device is operating as a virtual machine (VM mode flag 1 is "1") (in this example, This is a 2-bit register) and is output as the signal VMID. The exception detection means 3 is an exception detection circuit that detects memory access exceptions related to the instruction words and operands of instructions to be processed by the information processing device, and _exceptions generated by execution of instructions.
EX ₇ is output via signal line 300. The encoding means 4 is composed of an encoder 40 and registers 41 and 42, and outputs exception detection room numbers EX ₀ to EX ₇ to the encoder 40 via a signal line 300, and outputs an exception number en via a signal line 401. An exception valid signal v indicating that the exception number en is valid is outputted via the signal line 400. Exception valid signal v
is the logical sum of the exception signals _EX0 to _EX7 . Table 1 shows the relationship between the exception detection signals _EX0 to _EX7 and the exception number en.

[Table] Register 41 receives exception valid signal v from signal line 4
This is a 1-bit register that outputs a control storage activation signal V via 02. Register 42 is the exception number
This is a 3-bit register that receives en and outputs an exception number EN via signal line 403. exception number en
and exception number EN are the input signal and output signal of the register 42, and have the same value. The memory decoder 5 is given an address by the output signal VM of the VM mode flag 1, the output signal VMID of the VMID register 2, and the exception number EN of the register 42, and outputs an exception code exc via a signal 500. The exception code register 6 receives and holds the exception code exc output from the memory decoder 5, and the signal line 60
This is a register that outputs the exception code EXC to the outside via 0. exception code exc and exception code EXC
are the input signal and output signal of the exception code register 6, and their values are the same. The hold condition HD of the exception code register 6 is. The control storage means 7 includes a control storage 70, an address circuit 71, an address register 72, and a control register 73.
It consists of The address circuit 71 is a circuit that outputs the start address of a microprogram that performs exception processing in response to the control storage activation signal V, and sequentially outputs microinstruction addresses csa. Microprogram address cse is output via signal line 700. The address register 72 holds the microinstruction address CSA and outputs the microprogram address CSA to the signal line 70.
Output via 1. The control memory 70 stores a plurality of microinstruction words, and a microinstruction address.
Given an address by CSA, it outputs the corresponding microinstruction word. A control signal ct1 is outputted via a signal line 703, and an address na of a microinstruction to be executed next is outputted via a signal line 702. The control register 73 inputs the control signal CTL, and outputs the control signal CTL to the outside via the signal line 704.
This is a register that outputs. Table 2 shows the output signal VM of VM mode flag 1 and
Output signal VMID of VMID register 2 and register 4
2 shows the relationship between the exception number EN outputted by the memory decoder 2 and the output signal exc of the memory decoder 5.

【table】

〔Effect of the invention〕

As explained above, the present invention creates an exception code using the VM mode flag, VMID register, and exception number, thereby making it possible to recognize when the device is operating as a real computer and when it is operating as a virtual computer. It is possible to create exception codes with different architectures without having to do anything, and when operating as a virtual machine, it is possible to create exception codes with different architectures for each virtual machine identified by VMID. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing essential parts of an embodiment of an information processing apparatus of the present invention. 1...VM mode flag, 2...VMID register, 3...Exception detection means, 4...Encoding means, 5...Memory decoder, 6...Exception code register, 7...Control storage means, 40...Encoder , 41, 42...Register, 70...Control memory, 71...Address circuit, 72...Address register, 73...Control register, 300,400
~403,500,600,700~704...
Signal line.

Claims (1)

[Claims] 1. In a microprogram-controlled information processing device that uses a virtual computer method, a VM mode flag indicating whether the device is operating as a virtual computer and a virtual computer identification number indicating the type of virtual computer are provided. The VMID register that is held, the exception detection means that detects memory access exceptions related to the instruction word and operand of the instruction to be processed, and exceptions that occur due to instruction execution, and the exception detection signal detected by the exception detection means. a memory decoder that outputs an exception code given an address by the VM mode flag, VMID register, and exception number; and a memory decoder that stores the exception code output from the memory decoder. , an exception code register that is displayed externally, and a control memory that stores a plurality of microinstruction words and that sequentially outputs the microinstructions in response to an exception detection signal from the exception detection means. An information processing device characterized by: