JPH04116725A - Exception processing system - Google Patents

Abstract

PURPOSE:To speed up an exception processing by reading exception information corresponding to a detected exception from an exception table by means of compulsorily setting an exception number in an address register for which an exception representative flag is set. CONSTITUTION:A memory exception or an operation exception is detected and the content of an exception processing head address register 18 is set in the address register 21 by a cancel/update suppression signal 16. Then, an exception processing micro program is set in a read register 23 from a control storage device 22. At this time, exception information corresponding to an entry, namely, an exception number in the exception table for which SPA 28 shows from SPM 29. Thus, the exception processing can be speeded up since the interruption of the processing does not occur.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an exception handling method, and particularly to types of exceptions.

This invention relates to an exception handling method for quickly extracting exception information such as exception addresses and other parameters.

[Conventional technology]

When an exception occurs during instruction execution in an information processing device controlled by a microprogram, a microprogram is prepared in advance to handle the exception depending on the type of exception, and a predetermined program is created to handle each exception. It is controlled so that the following processing is performed. In general, exceptions can be broadly classified into inhibited exceptions and completion-type exceptions, and exceptions related to instruction formats and exceptions that occur during memory operand access mainly belong to the inhibited type. In the case of a suppressed exception, the processing method is to wait for the completion of the preceding instruction, suppress the updating of the own instruction, and then cancel the subsequent instruction. On the other hand, completed-type exceptions mainly include exceptions related to operations, and are a processing method that does not prevent updates when an exception occurs in the operation result, but instead completes the instruction and cancels subsequent instructions. be.

In any case, when an exception is detected, a microprogram intervenes to perform the specified processing.
A pre-prepared exception handling microprogram is activated, but in the case of a suppressed exception, it waits for the completion of the preceding instruction, and in the case of a completed exception, it is activated when it is detected, and each exception handling microprogram is activated. runs and reports exception information (exception type 1 exception address, other parameters, etc.) to ○S. Since the contents of the exception information differ depending on the exception, the exception information corresponding to each exception is stored as a table, and in the prior art, this table is stored in the main memory.

Conventionally, the configuration of an exception handling method for extracting exception information was
It was as shown in the figure.

Generally, when the exception detection circuit 51 detects an instruction format-related exception that is a suppressed exception and an exception that occurs during memory operand access, the priority encoder circuit 52 stores the exception number of the exception with the highest priority in the exception detection register. 53, and at the same time, the exception representative bit 54 is set. Either the exception detection register 53 and the exception representative bit 54 or the memory exception buffer 55 are set in the memory exception register 57 and the exception representative bit 58 by a simultaneous command which is a microinstruction or an instruction. The memory exception buffer 55 is for synchronization, and when a synchronization command is issued, if the exception buffer 55 is empty, the exception representative bit 54 of the exception detection register 53 is set, and if it is not empty, the memory exception buffer The contents of 55 are selected by selector 56 so as to be set in memory exception register 57 and exception representative bit 58.

On the other hand, when an exception related to an operation, which is a complete type exception, is detected by the operation exception detection circuit 60, it is set in the exception detection register 61, and then the exception with the highest priority is set by the priority encoder circuit 62. The exception number is set in the arithmetic exception register 63, and at the same time the exception representative bit 44 is set.

The above two registers, the memory exception register 57 and the operation exception register 63, each have an exception representative bit 58.
When the exception representative bit 64 is set, its value is held until a clear instruction is issued by a microinstruction.

The exception representative bit 58 is once received as five exception representative bits in order to suppress updating after waiting for the completion of the preceding instruction. 5 exception representative bits or 64 exception representative bits
When is set, a cancel and update inhibit signal 66 is generated that cancels subsequent instructions and inhibits updates, and the contents of registers other than the memory exception register 57 and the operation exception register 63 are cleared. In addition, this signal is once received by the forced set signal register 67, whereby the contents of the exception processing start address register 68 (fixed address) in which the start address of the exception processing microprogram is stored in the address register 71 are forcibly set. After that, the exception handling microprogram is executed.

In a microinstruction, the contents indicated by the address register 71 are read from the control storage device 72, set in the readout register 73, and executed. The contents of the field indicating the next address in the program are set in the address register 71, and the microprograms are sequentially read out and executed. Furthermore, the start address of the next instruction is set in the next instruction start address register 70 by advance control, and when the preceding instruction ends, it is set in the address register 71, and the microprogram of the next instruction is read and executed. If there is an interrupt, the contents of the interrupt start address register will be set in the address register 71.

In the exception processing microprogram, first, the memory exception register 57 sets the contents (exception number) of one of the operation exception registers 63 to the operand register 76. The exception representative bit 64 is used as the selection signal, and when the exception representative bit 64 is set, the arithmetic exception register 63 is selected, and otherwise the memory exception register 57 is selected by the selector 65. This means that when five exception representative bits and exception representative bit 64 are set at the same time,
The exception representative bit 64 is used as a selection signal because the modulus of the operation exception is an exception due to a preceding instruction.

Next, the contents of the exception table start address register 80, which has the start address of the exception table stored seven places above the main memory, are set in the operand register 277. The exception table is prepared in the main memory, and the entries in the exception table are 4-byte data.The contents include the class and type of the exception to be reported to O8, and information indicating whether it is a machine malfunction/illegal exception/functional exception. , and information indicating the notification method of either process notification or system notification.

The address of the exception table entry indicated by the exception number is
Calculated by arithmetic unit 74. That is, the calculation (start address of exception table) + (exception number) x 4 is performed and the result is stored in the calculation result register 75. The contents of this register are input to the memory operand retrieval control unit 78, an effective address is generated by the effective address generation circuit, an address in the main memory where the exception information is stored is generated by the real address conversion circuit, and the operand is retrieved. In the circuit, the exception information corresponding to the exception number is retrieved from the exception table on the main memory and is stored in the operand register 7.
6 or operand register 77, and set this to o
Report to S.

[Problem to be solved by the invention]

In the conventional exception handling method described above, a register indicating the start address of the exception table is used to retrieve the exception information corresponding to the exception number, and the address of the entry on the exception table is calculated based on this and the exception number. Since the exception information must be retrieved from the main memory using this address after performing arithmetic processing, it takes time. Therefore, even if the exception processing address is forcibly set in the address register by the cancel and update inhibition signal 66 and the exception processing microprogram is read from the control storage device 72 and set in the read register 73, the exception information may not be read from the exception table. state,
Processing is suspended until the exception information is read, resulting in a reduction in performance.

[Means to solve the problem]

The exception handling method of the present invention detects an exception regarding an operand, an instruction word, or an operation using hardware or a microprogram, and processes the exception using the microprogram. means for generating an exception representative flag indicating that an exception has been detected and an exception number indicating the type of exception; an exception table storing exception information corresponding to the exception number for processing the exception in a microprogram; An address register is provided for indexing, and when the exception representative flag is set, the exception number is forcibly set in the address register, and the exception information corresponding to the detected exception is read from the exception table and configured. .

〔Example〕

Next, the present invention will be explained with reference to FIG.

In Figure 1, the exception table is set to SPM (Sflitch).
pad memory) two lower halves (100 to 25 of IFF
6 words x 4 bytes), and 5PA (scratch pad memory address register) 28 (9 bits) is provided as an address for indexing this. In addition, the upper half of sPM 24 (000 to OFF 2
56" (7-dore x 4 bytes) is used as normal memory.

Exceptions related to instruction formats and exceptions that occur during memory operand access tend to be detected before they are set in the memory exception register 7, and exceptions related to operations are detected and set in the arithmetic exception register 13. It is controlled in the same way as the prior art.

In the present invention, exception representative bit 9 or exception representative bit 14
When is set, a cancel and update inhibit signal 16 is generated that cancels subsequent instructions and inhibits updates, and the contents of registers other than the memory exception register 7 and the operation exception register 13 are cleared. Additionally, this signal is once received by the forced set signal register]-7, and thereby the contents of the exception handling start address register 18 (fixed address), which stores the start address of the exception handling microprogram in the address register 21, are forcibly set. , after which the exception handling microprogram is executed. Furthermore, the cancel and update inhibit signal 16 sets the contents of either the memory exception register 7 or the operation exception register 13 (exception number 8 bits) in the SPA, and at the same time sets the most significant bit to 1. Note that O is normally set in the most significant bit. Once set, SPA 28 registers memory exception register 7 and arithmetic exception register 13.
Similarly, the value is held until a clear instruction is issued by a microinstruction. The memory exception register 7 and the calculation exception register 13 are selected by the exception representative bit 14. When the exception representative bit 14 is set, the calculation exception register 13 is selected, and if not, the memory exception register 7 is selected by the selector 15. .

As described above, a memory exception or an operation exception is detected, the contents of the exception processing start address register 18 are set in the address register 21 by the cancel and update inhibition signal 16, and the exception processing microprogram is read from the control storage device 22 and set in the register 23. When it is done,
Exception information corresponding to the entry in the exception table indicated by SPA 28, that is, the exception number, is read from SPM 29 at all times, and the processing is not interrupted as in the prior art, so exception processing is speeded up. .

〔Effect of the invention〕

As explained above, in the present invention, when a memory exception or an arithmetic exception is detected and the exception processing microprogram is set in the read register, the exception information corresponding to the exception number of the detected exception is already read from the exception table on the SPM. This eliminates the problem of interrupting processing until exception information is obtained, which was the case with the prior art, and has the effect of speeding up exception processing.

Interrupt start address register, 20...
・Next instruction start address register, 21... Address register, 22... Control storage device, 23... Read register, 24... Arithmetic unit, 25... Operation result register, 26, 27... Operand Register, 28...
SPA, 29...SPM.

Claims (1)

[Claims] In a microprogram control device that detects an exception related to an operand, an exception related to a command word, or an exception related to an operation using hardware or a microprogram, and processes the exception in the microprogram, an exception is generated when an exception is detected. Means for generating an exception representative flag indicating that the exception has been detected and an exception number indicating the type of exception, an exception table storing exception information corresponding to the exception number for processing the exception in a microprogram, and indexing the table. The invention is characterized in that when the exception representative flag is set, the exception number is forcibly set in the address register, and the exception information corresponding to the detected exception is read from the exception table. Exception handling method.