JPH0769816B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a data processing device having a mechanism for processing calls and returns of subroutines at high speed.

2. Description of the Related Art As a conventional data processing device, for example, JP-A-62-28514 is used.
This is shown in Japanese Patent Publication No. 0. FIG. 4 shows the configuration of a conventional data processing device. 100 is a stack control unit, 101
Is an address stack, 102 is an instruction stack, 103 is a next instruction address register, 104 is an address selector, 105 is an instruction buffer holding a plurality of instructions by preceding fetch, 106 is an instruction selector, and 107 is an increment for adding instruction addresses. Reference numeral 108 is an aligner for cutting out an instruction from the instruction buffer 105, 109 is an instruction register, 110 is a register file, 111 is a comparator, 112 is a cache, and 113 is a decoder for decoding instructions.

The operation of the conventional data processing apparatus configured as above will be described below.

The instruction buffer 105 holds the instruction string fetched in advance from the cache 112. An instruction is cut out from the instruction buffer 105 by an aligner 108 controlled by the value of the next instruction address register 103 and supplied to the instruction register 109. Decoder 1 for instructions stored in instruction register 109
Decode at 13 to control instruction execution. The value of the next instruction address register 103 is added by the incrementer 107 to indicate the next instruction address.

When the decoder 113 detects a call instruction for making a subroutine call, it notifies the stack control unit 100 of the detection of the call instruction, and the stack control unit 100 causes the instruction buffer 1
The contents of 05 are pushed onto the instruction stack 102, the value of the next instruction address 103 is pushed onto the address stack 102, and the instruction stack including the instruction following the call instruction and the address indicating the beginning of the instruction stack are the instruction stack 102 and the address stack 101. Are evacuated to.

Whenever a call instruction is detected, an instruction sequence and an address are pushed onto the instruction stack 102 and the address stack 101, and when the stack capacity is exceeded, the instruction sequence and address are discarded from the bottom. That is, as many sets of instruction strings and addresses are held as the number of nests determined by the stack capacity. Also, the return address is stored in the register file 110 when the call instruction is executed.

When the decoder 113 detects a return instruction for performing a subroutine return, the stack control unit 100 is notified of the detection of the return instruction. The stack control unit 100 reads an address from the stack top of the address stack 101, and the comparator 111 determines whether or not the address matches the address stored in the register file 110. If they match, the instruction sequence of the return destination is held at the top of the instruction stack 102, so the instruction stack 102
The instruction string is popped from the stack top of the above to the instruction buffer 105, and the next instruction address is popped from the stack top of the address stack 101 to the next instruction address register 103. In this way, the instruction sequence including the instruction following the call instruction saved at the time of the subroutine call is returned to the instruction buffer 105 at the time of the subroutine return, and is interrupted by the call instruction using the value of the next instruction address 103 which is also returned. The executed instruction sequence can be executed.

Through the above operation, the call / return processing of the subroutine is speeded up.

However, the above-described configuration is not effective in speeding up the instruction branching by executing the call instruction, and the decoder 11
Since the return instruction is detected in step 3, there is a problem that it takes one clock or more to execute the return instruction no matter how high the speed.

In view of the above point, the present invention has an object to provide a data processing device which executes call / return processing of a subroutine at an extremely high speed by executing a call instruction and a return instruction at 0 clock. .

Means for Solving the Problems The present invention provides a data processing apparatus for pipeline processing instruction execution, a branch destination instruction branched to by a call instruction or a return instruction, a branch destination next instruction address, a call instruction or a return instruction. Branch destination information including a stack pointer value after instruction execution is held, and branch destination information holding means having a program counter value and a stack pointer value as a key for searching the branch destination information is provided, and the held branch destination information The branch destination information without waiting for the execution processing of the call instruction or the return instruction by searching with the values of the program counter and the stack pointer of the cycle one cycle or more before the execution processing of the call instruction or the return instruction as a key. The data processing device is characterized in that branch destination information is supplied from a holding unit.

According to the present invention, by the above-described means, the branch destination information holding means is searched, and the information of the branch destination instruction sequence by the subroutine call and the return destination instruction sequence by the subroutine return are searched without decoding the call instruction and the return instruction. Information can be obtained, and the call instruction and the return instruction can be effectively executed in 0 clock. Recursive calls can be dealt with by searching the branch destination information holding means with a pair of a program counter and a stack pointer.

Embodiment FIG. 1 is a block diagram of a data processing device in an embodiment of the present invention. In FIG. 1, 1 is an instruction cache, 2 is an instruction register, 3 is a decoder, 4 is an instruction execution unit, 5 is a prefetch counter (PFC) indicating an address of an instruction fetched from the instruction cache, and 6 is an incrementer for adding PFC. , 7 is the program counter (PCD) of the decoding unit that indicates the address of the instruction stored in the instruction register, 8 is the stack pointer (SP), 9 is the copy of the stack pointer (SPD), and 10 is the update of the copy of the stack pointer. SPD control unit to control, 11 is a comparator, 12 is a call to search by PCD and SPD by holding the address of the first instruction of the branch destination when branching by call or return, the address of the instruction following and the SPD at the time of branching Return buffer, 13 is a return address rewrite detection unit, 14, 15, 16 are selectors for switching to the data from the call / return buffer 12, 1 7 is a general-purpose register.

The operation of the present embodiment configured as described above will be described below.

In the data processing apparatus according to the present embodiment, instruction execution is processed by the instruction fetch (IF), decode (DEC), data read (R), execution (EX), and data write (W) pipelines. That is, in the instruction fetch stage, the instruction of the address indicated by PFC5 is fetched from the instruction cache 1 and sent to the instruction register 2 through the selector 15, and the instruction of the instruction register 2 is decoded and executed by the execution unit 4 in the next decode stage. To control. The execution unit 4 reads data from the general-purpose register 17 in the data read stage, performs arithmetic in the execution stage, and writes the result in the data write stage. In the case of memory access, address calculation is performed in the execution stage, and memory access is performed in the data write stage.

SPD9 is a copy of stack pointer SP8, and SPD controller
SPD9 update is controlled by 10. SPD control unit 10
In addition to the control to write the value of SP8 to 9 or the value from the call / return buffer 12, the control to suppress the update of the fixed cycle SPD when the value from the call / return buffer 12 is written To do.

In the decode stage, SP is executed in parallel with instruction decoding.
The call / return buffer is searched with the value of D9 and the value of PCD7. When the call / return buffer is hit,
By controlling the selectors 15, 14 and 16, the call / return buffer 12 sends the branch destination instruction to the instruction register 2, the branch destination next instruction address to PFC5, and the branch destination SPD value to SPD9. That is, when a call instruction or a return instruction is executed in the past and is registered in the call / return buffer 12, and the same call instruction or a return instruction is executed again, the call / return buffer 12 is searched when the immediately preceding instruction is decoded. This makes it possible to supply the information of the branch destination instruction sequence branched by the call instruction or the return instruction without executing the call instruction or the return instruction itself.
This operation will be described in more detail below.

In this embodiment, as an example of the call / return sequence, a case where the routine B is called by the bsr instruction from the routine A, the routine B is executed and then the routine A is returned by the rts instruction is given.

As an example of returning from routine B in FIG. 2,
The following shows the operation timing when there is no branch destination information in the call / return buffer. Instruction in parallel with decoding of instruction B2
The call / return buffer 12 is searched by the value of PCD7 which is the address of B2 and the value of SPD9 at that time. When the call / return buffer 12 has a mishit, the rts instruction sent from the instruction cache 1 is selected by the selector 15 and stored in the instruction register 2 to flow below the decode stage. rt
s instruction pops return address from stack and PFC
By storing the return address in 5, it is possible to process the instruction at the return destination. During this time SPD control unit 10
Copies the value of SP9 to SPD9 every machine cycle. When a miss hit occurs, the call / return buffer 12 creates an entry with the SPD and PCD values used for the search as tags, and the return destination instruction A in the data part of the entry.
1. The address of the return destination next instruction A2 and the value of PCD7 when the return destination instruction A1 is being decoded are stored as they are determined.

Next, the operation when the call / return buffer 12 is hit is shown in FIG. Information on the return destination is registered in the call / return buffer 12 by the operation shown in FIG. In parallel with the decoding of the instruction B2, the call / return buffer 12 is searched by the value of PCD7 which is the address of the instruction B2 and the value of SPD9 at that time. When the call / return buffer 12 hits, the selectors 15, 14 and 16 are controlled so that the call / return buffer 12 returns the return destination instruction A1 to the instruction register 2, the return destination next instruction A2 address to PFC5, and the return destination instruction. The SPD value when A1 is decoded is sent to SPD9.

Therefore, as the instruction flow, the return destination instruction A1 is executed next to the instruction B2 immediately before the return instruction in the routine B. That is, the return instruction rts is effectively executed in 0 clock. Here, the update of SPD9 is suppressed by the SPD control unit 10 until the execution of the return destination instruction A1 is completed. This is to match the change in SPD9 when the call / return buffer 12 is hit.

Here, the operation of the call / return buffer 12 has been described by taking the case of the return instruction as an example, but similarly, in the case of the call instruction, the operation can be effectively executed with 0 clock. However, in the case of a call instruction, in addition to the processing of the return instruction, the return address rewrite detection unit
Register the address of the stack that stores the return address in 13. The return address rewrite detection unit 13 monitors the writing to the stack, and when the writing to the return address storage location is detected, the call / return buffer 12 is completely purged to prevent runaway of the program.

As described above, according to this embodiment, when the same call / return sequence is performed, by registering the information of the branch destination instruction sequence branched by the call instruction or the return instruction in the call / return buffer 12, The return instruction can be executed in 0 clock, and the call / return can be processed at high speed. Further, since the copy of the program counter and the stack pointer is used as the information for searching the call / return buffer 12, recursive calls can be dealt with.

As described above, according to the present invention, regardless of the form of the call / return sequence such as recursive call, when the call instruction or the return instruction which has been executed once is executed again, the branch destination information holding means is provided. As long as it is stored, by using the information, the return instruction and the call instruction can be effectively executed with 0 clock, so that the call sequence and the return sequence can be processed at a high speed. Effect is large.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, and FIG.
3 and FIG. 3 are timing charts for explaining the operation of the embodiment.
FIG. 4 is a block diagram of a conventional example. 1 ... Instruction cache, 2 ... Instruction register, 3 ... Decoder, 4 ... Execution unit, 5 ... Prefetch counter (PFC), 6 ... Incrementer, 7 ... Program counter, 8 ... Stack pointer ( SP), 9 ... Copy of stack pointer (SPD), 10 ... SPD control unit, 11 ...
Comparator, 12 ... Call / return buffer, 13 ... Return address rewriting detection unit, 14, 15, 16 ... Selector,
17 …… General purpose register, 100 …… Stack control block, 101 ……
Address stack, 102 ... Instruction stack, 103 ... Next instruction address register, 104 ... Address selector, 105 ...
… Instruction buffer, 106 …… Instruction selector, 107 …… Incrementer, 108 …… Aligner, 109 …… Instruction register, 11
0 …… Register file, 111 …… Comparator, 112 …… Cache, 113 …… Decoder.

Claims (1)

[Claims] 1. A data processing device for pipelined execution of instructions, a branch destination instruction branched to by a call instruction or a return instruction, a branch destination next instruction address, and a stack pointer after execution of the call instruction or the return instruction. And branch destination information holding means having a program counter value and a stack pointer value as a key for searching the branch destination information, and the held branch destination information is a call instruction or a return instruction. Is executed by using the program counter and the value of the stack pointer of the cycle one cycle or more before the execution processing as a key, and the branch destination information holding means stores the branch destination information without waiting for the execution processing of the call instruction or the return instruction. A data processing device, characterized in that