JP3317985B2 - Pseudo vector processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly, to a technique for enabling a data processing apparatus to access more registers than the number of registers addressable by an instruction. In particular, by doing so, so-called vector processing for continuously processing large-scale data for which the cache is not very effective,
The present invention relates to a technique which makes it possible to hardly cause a decrease in performance for transfer from a main memory and to realize efficient pseudo vector processing with a normal data processing device.

[0002]

2. Description of the Related Art Conventionally, as a technique for enabling a data processing device to access more registers than the number of registers addressable by an instruction, Japanese Patent Laid-Open No.
According to this method, first, a register group called a hardware register is provided which is larger than the number of general-purpose registers addressable by a program, and a plurality of registers for the same general-purpose register are provided from different main memory addresses. Are stored in the hardware register as many as the number of the load instructions (that is, the number of the load instructions).
If the number of general-purpose registers that can be addressed by the program is 16, hardware registers are prepared for each general-purpose register, that is, a total of 256 hardware registers.
The hardware registers 0 to 15 are assigned to the general-purpose register 0. When a load instruction specifying 16 different main storage addresses is executed for general-purpose register 0, data from the 16 load instructions is transferred from hardware register 0 to hardware register 0. The data is stored in the hardware register 15). A storage mechanism is provided for registering a main memory address of a previously executed load instruction and a hardware register number in which data loaded at that time is stored. If the load instruction matches the main memory address registered in the storage mechanism, the data is read from the corresponding hardware register without reading the data from the main memory. According to this method, the number of times of referring to the main memory can be reduced, and performance degradation due to collision of the reference register between instructions can be prevented.

(Prior Art 2) Conventionally, as a technique for enabling a data processing device to access more registers than the number of registers addressable by an instruction, J. L. Hen
nessy and D.S. A. Patterson "
ComputerArchitecture: A
QuantitativeApproach ", Mo
rgan Kaufmann Publish-er
s, Inc. (1990). According to this method, first, a register called a physical register that is larger than the number of registers addressable by a program is provided, and the physical register is divided into a plurality of windows. That is, each window is composed of a plurality of physical registers. For example, it is assumed that registers are numbered from number 1 to n by a program, and that n * m physical registers, that is, numbers 1 to n * m are provided. Assuming that there are m windows, that is, numbers 1 to m, window 1 is assigned to physical register 1
To n, window 2 can be assigned as physical registers n + 1 to 2n, and so on. In practice, it is customary to provide a physical register common to all windows, a physical register common to adjacent windows, and the like. However, for simplicity, the above example is shown. Each window has registers used by one program. In other words, referring to a register that can be addressed by a certain program actually refers to a physical register belonging to a certain window. For example, in the above example, if window 2 is assigned to a certain program, if the register k is specified in the program, the physical register to be referred to is the physical register n + k.

This window is used as follows. If window j is allocated to a certain program, the program calls another program (cal
l), the called program contains a window j
+1 is assigned. If window j is allocated to a certain program, if the program returns to the program that called the program (returned), the window j-1
Is assigned. By using in this way, the following effects are obtained. In a system having only as many registers as the number of registers that can be addressed by a program, each time a program call as described above occurs, the data stored in the register is used to save information at the time of the call. Must be stored in the main memory, and every time the program returns, the data stored in the main memory must be written back to the register in order to restart the program. In a system having the above window mechanism, since a program to which a different window is assigned refers to a different physical register, the operation of storing data from the above-mentioned register to the main memory and writing back from the main memory to the register is performed. Becomes unnecessary, and the processing speed is increased.

[0005] However, in a system having the window mechanism, when a program call is issued from the program having the largest window number, the window overflow is performed.
When the program returns from the program with the smallest window number, a window underflow interrupt is caused. "

[0006]

The majority of scientific and technical calculations are vector operations as described below.

C (i) = A (i) + B (i) i = 1, N (1) Here, A, B, and C are vectors having N elements.

When equation (1) is executed by a general-purpose computer, a program as shown in Table 1 is obtained.

In the following description, a floating-point register storing a floating-point number is taken as an example, and it is assumed that the data width of the floating-point register is 8 bytes.

The function of each instruction in Table 1 will be described below.

FLDM a (GRm), FRn (Function) 8-byte data is read from the main memory address represented by the value of the general-purpose register m and stored in the floating-point register n.

Thereafter, the value of the general-purpose register m is added by a.

FADD FRj, FRm, FRn (Function) The value of the floating-point register m and the value of the floating-point register n are added and stored in the floating-point register j.

FSTM a (GRm), FRn (Function) Stores the value (8 bytes) of floating-point register n in the main memory address represented by the value of general-purpose register m.

Thereafter, the value of the general-purpose register m is added by a.

BCNT GRm, t (Function) Decreases the value of GRm by one. If the value is not zero, branch to address t. If zero, do not branch.

[0017]

[Table 1]

Here, it is assumed that prior to the execution of the program shown in Table 1, the vector A is stored in a continuous area starting from the main storage address ad1. That is, A
The main storage address of (1) is stored as ad1, and the main storage address of A (2) is stored as ad1 + 8. Similarly, it is assumed that the vector B is stored in a continuous area starting from the main storage address ad2. Also, the vector C
Is stored in a continuous area starting from the main storage address ad3. It is assumed that ad1 is stored in general-purpose register 1, ad2 is stored in general-purpose register 2, ad3 is stored in general-purpose register 3, and N is stored in general-purpose register 4 in advance.

As can be seen from Table 1, no. 1, No.
A (i) and B (i) are loaded into the floating point registers 12 and 13 respectively by two FLDM instructions, the values of the two registers are added and stored in the floating point register 20,
The contents of the register are stored in C (i).

That is, by executing a loop consisting of five instructions once, a result of one element is obtained.
By executing the loop N times, all element calculations can be performed.

The problem here is the execution time of one loop. First, no. 1 and No. Load data from main memory to floating point registers 12 and 13 by FLDM instruction 2
FLD when there is data in the cache
The M instruction ends in a short number of cycles, but if it is not in the cache, the data is taken from main memory, which is much slower than the cache.
The data must be read out, which takes much longer than when data is in the cache. Then N
o. 3 FADD instructions are floating point registers 12 and 13
Since the values of the floating point registers 12 and 13 are not determined until the execution of the preceding two FLDM instructions is completed, that is, the data reading is not completed, the FADD instruction Execution cannot be started until. In addition, No. The FSTM instruction of No. 4 uses the value of the floating-point register 20, but the value of the floating-point register 20 cannot be determined until the execution of the preceding FADD instruction is completed, so that the execution of the FSTM instruction cannot be started until then. That is, (1) the data read time and (2) the collision of the registers, two performance degradation factors increase the execution time of the loop. In particular, the case (1) is serious in the case of calculation for handling long data, and since the required data often cannot be stored in the cache, the performance is greatly reduced.

One method for solving this problem is loop unrolling, which is shown in Table 2. That is, 1
In this method, a plurality of elements (= n) are processed in a loop, and the number of loops is reduced to 1 / n as compared with a case where one element is processed in one loop. Table 2 shows a method for processing four elements in one loop.

[0023]

[Table 2]

Here, it is assumed that the vector A is stored in a continuous area starting from the main storage address ad1 prior to the execution of the program shown in Table 2. That is, A
The main storage address of (1) is stored as ad1, and the main storage address of A (2) is stored as ad1 + 8. Similarly, it is assumed that the vector B is stored in a continuous area starting from the main storage address ad2. Also, the vector C
Is stored in a continuous area starting from the main storage address ad3. It is assumed that ad1 is stored in general-purpose register 1, ad2 is stored in general-purpose register 2, ad3 is stored in general-purpose register 3, and N / 4 is stored in general-purpose register 4 in advance.

As can be seen from Table 2, by executing a loop consisting of 17 instructions once, a four-element result is obtained, and by executing this loop N / 4 times, all elements can be calculated. .

As can be seen from Table 2, for the i-th element, the load is No. 1 and No. In the FLDM instruction of No. 2, the addition is No. 9 is stored in No. 9 by the FADD instruction. 13 FSTM instructions. Similarly, for the (i + 1) th element, the load is set to No. 3 and No. No. 4 FLDM instruction, the addition is No. With the FADD instruction of No. 10, the store is No. 14
FSTM instruction. Similarly, regarding the (i + 2) th element, the load is set to No. 5 and No. 5 No. 6 with the FLDM instruction No. 6 11, the store is No. 11 by the FADD instruction. Fifteen
FSTM instruction. Similarly, with respect to the (i + 3) th element, the load is No. 7 and no. No. 8 with the FLDM instruction No. 8 No. 12, the store is No. 16
FSTM instruction. Therefore, as compared with Table 1, loading, addition,
A series of processes called store are separated on the instruction sequence, and the effects of the two performance degradation factors (1) data read time and (2) register collision can be reduced. For example, No. 1 and No. A with 2 FLDM instructions
Loading of (i) and B (i) is performed, and the loading result is used after 7 instructions. If the data reading time is within 7 cycles, the loading is performed. Use result N
o. Nine FADD instructions are not awaited. Also,
No. 9 Addition result A (i) + B by FADD instruction
Since (i) is used after four instructions, if the time required for addition is within four cycles, No. 13 FSTs
There is no waiting for the M instruction.

Although loop unrolling improves performance, the disadvantage of this scheme is that it requires many registers. The program in Table 1 requires three floating point registers, while the program in Table 2 requires twelve floating point registers. If the time required for reading the data is longer or the time required for the operation is longer, more elements must be processed in one loop and more registers are required. Will be.

Generally, a register is made up of active elements (ie, not memory elements),
Port for writing (ie, data entry / exit)
Can be prepared, so that the speed of the storage device is much higher than that of a storage device which can only read / write one piece of data in one operation cycle. Therefore, it is indispensable to have a register with a sufficient capacity for speeding up, not only the main memory but also the cache. Nevertheless, conventionally, the number of registers was relatively small because of the high cost per bit and the restriction on the length of the register number field in the instruction format as shown below. Because there was. Although the problem of cost is being solved by LSI,
The latter was still unresolved.

The number of registers that can be addressed by a program is limited in terms of architecture. For example,
If there are 5 bits in the register specification field in the instruction word,
The number of addressable registers is 32 (2 to the fifth power). Increasing the number of bits in the register specification field increases the number of registers that can be addressed by the program, but changes the instruction format, which requires modification of the existing program, which is impractical.

Therefore, it is necessary to provide a system in which the data processing device can access more registers than the number of registers addressable by the instruction without changing the architecture of the data processing device. In 1, when a new load instruction is issued for a main memory address where a load instruction was executed in the past, the speed is increased. However, in many cases, the vector calculation as in the equation (1) requires only one load request for the data in the main memory as in the programs shown in Tables 1 and 2. There is a problem that is not done.

Further, in the prior art 2, only one physical register belonging to a certain window can be used in one program, and the number thereof is equal to the number of registers addressable by the program, and the number of operations performed by one program is one. Can not speed up. In other words, the above-mentioned window mechanism speeds up the processing only when a program call and return occur.
When the processing is completed in one program, there is a problem that the speed is not increased. Also, the interruption of the window overflow and the window underflow is not necessary when the processing is completed by one program as in the vector calculation of the equation (1) and no call and return of the program occur. There is a problem that there is.

An object of the present invention is to make it possible for a data processing device to access more registers than the number of registers addressable by an instruction without changing the architecture of the data processing device, and to provide a vector for scientific calculation. An object of the present invention is to provide a method for performing calculations at high speed.

[0033]

In order to achieve the above object, there is provided a floating point register called a physical floating point register having more than the number of floating point registers addressable by an instruction, wherein the register is a physical floating point register number. Will be referred to by In addition, the entire physical floating-point register is divided into a partial group consisting of a plurality of registers called a window, so that the register can be referred to by a combination of a window number and a register number in the window. In order to determine these correspondences, a current floating point window pointer, which stores a current floating point window pointer indicating a pattern for converting a floating point register number in a program instruction into a physical floating point register number, which is called a logical floating point register number, is used. Decimal point window pointer register, current floating point window pointer valid register that stores a value indicating that the current floating point window pointer is valid, logical floating point register number using the current floating point window pointer, physical floating point register number A floating-point window pointer change instruction for changing the current floating-point window pointer, and a logical floating-point register number determined from the current floating-point window pointer, but different from the current floating-point window pointer. Main memory de values to the physical floating point register obtained by converting the current floating point window pointer - floating point register preload to store data -
The instruction and logical floating-point register number are determined from the current floating-point window pointer, but data different from the current floating-point window pointer are converted to the current floating-point window pointer as data from the physical floating-point register and data is stored in the main memory. Provide a floating-point register post-store instruction to store.

[0034]

[Effect] In all instructions that refer to the floating-point register,
The value of the current floating-point window pointer valid register is 1
If, the logical floating-point register number-physical floating-point register number conversion is performed, and the physical floating-point register number is referred to by referring to the floating-point register. If the value of the current floating point window pointer valid register is 0, the logical floating point register number is equal to the physical floating point register number.

The conversion of the logical floating-point register number to the physical floating-point register number is performed as follows. A plurality of types are provided for specifying which range of the physical floating-point register the logical floating-point register specifies. The specification of this range is the above-mentioned window.

FIG. 1 shows an example of how to provide a window. In this example, there are 32 logical floating point registers, and logical floating point register numbers 0 to 31 can be specified. There are 88 physical floating point registers, and physical floating point register numbers are 0 to 87. The window is w
0 to w3 are provided, and are designated by the current floating point window pointers 0 to 3, respectively.

Here, the current floating-point window pointer is denoted by w, the logical floating-point register number is denoted by r, and the physical floating-point register number is determined by w and r.
w, r>.

An instruction is used to increase or decrease w, and the increase or decrease is performed modulo 4. For example, when w = 3, the value of w + 1 is 0.

In the example of FIG. 1, the conversion of the logical floating point register number to the physical floating point register number is performed as follows.

1. When 0 ≦ r ≦ 7: <w, r> = r regardless of w (2) When 8 ≦ r ≦ 31: <0, r> = r (3) <1, r> = r + 20 (4) <2, r> = r + 40 (5) <3, r> = r + 60 (8 ≦ r ≦ 27) r-20 (28 ≦ r ≦ 31) (6) The following two features are characteristic of the above conversion method.

1. The physical floating point registers 0 to 7 are used in common for each window. These registers hold, as global registers, data common to the operation loop using each window.

2. The logical floating point registers 28 to 31 of each window indicate the same physical floating point registers as the logical floating point registers 8 to 11 of the window whose current floating point window pointer is one larger. These registers are overlap regis
It is used to transfer data between operation loops using adjacent windows as ter.

The instruction mnemonics and functions of the new instruction are as follows:
As an example, it is determined as follows.

1. Current floating-point window pointer change instruction (instruction mnemonic) CFRWPS GRm (Function) Sets the value of the general-purpose register m to the current floating-point window pointer register. 2. Floating point register preload instruction (instruction mnemonic) FLDPRM a (GRm), FR
n (Function) Reads 8-byte data from the main memory address represented by the value of the general-purpose register m and stores it in the floating-point register n. At this time, logical floating-point register number-physical floating-point register number conversion is performed using (current floating-point register window pointer + 1) as the current floating-point register window pointer.

Thereafter, the value of the general-purpose register m is added by a.

3. Floating-point register post store instruction FSTPOM a (GRm), FRn (Function) Stores the value (8 bytes) of floating-point register n at the main memory address represented by the value of general-purpose register m. At this time, logical floating point register number-physical floating point register number conversion is performed using (current floating point register window pointer-1) as the current floating point register window pointer.

Thereafter, the value of the general-purpose register m is added by a.

In addition, a general floating-point instruction (ie,
In the floating-point instructions except for the above 2-3, the logical floating-point register number-physical floating-point register number conversion is performed using the current floating-point register window pointer.

When the above-mentioned new function is used for the expression (1), a program as shown in Table 3 is obtained.

Here, it is assumed that the vector A is stored in a continuous area starting from the main storage address ad1 prior to execution of the program shown in Table 3. That is, A
The main storage address of (1) is stored as ad1, and the main storage address of A (2) is stored as ad1 + 8. Similarly, it is assumed that the vector B is stored in a continuous area starting from the main storage address ad2. Also, the vector C
Is stored in a continuous area starting from the main storage address ad3. It is assumed that N-2 is stored in the general-purpose register 4, 1 is stored in the general-purpose register 5, 0 is stored in the general-purpose register 6, and 0 is stored in the current floating-point register window pointer register.

Here, Table 3 shows ADs that are not described above.
Since the D instruction is included, the function of the instruction will be described below.

ADD GRj, GRm (Function) Adds the value of general-purpose register j and the value of general-purpose register m and stores the result in general-purpose register j.

[0053]

[Table 3]

Table 3 will be described below. No. In the FLDM instruction of No. 1, the conversion of the logical floating-point register number to the physical floating-point register number is performed by the current floating-point register window pointer, so that A (1) is stored in the physical floating-point register <0, 12>. Similarly N
o. B (1) is stored in the physical floating point register <0, 13> by the second FLDM instruction. No. 3 FLDPR
In the M instruction, since the logical floating-point register number-physical floating-point register number conversion is performed using the value of "current floating-point register window pointer + 1", A (2) is stored in the physical floating-point register <1, 12>. You. Similarly, no. By the FLDPRM instruction of No. 4, B (2) is stored in the physical floating-point register <1, 13>. No. In the FADD instruction No. 5, the logical floating-point register number-physical floating-point register number conversion is performed by the current floating-point register window pointer, so that the values of the physical floating-point registers <0, 12> and the physical floating-point registers <0,
13> is added to the physical floating-point register <0,
20>. No. 1, No. A (1) and B (1) are respectively the physical floating point registers <0, 12> and the physical floating point registers <0, 13
>, A (1) + B (1) is stored in the physical floating point register <0, 20>. No. No. 5 ADD instruction and No. 5 The current CFP register window pointer is incremented by one by the CFWWPS instruction of No. 6 to be 1. No. No. 8 to No. 8 FLDPRM instruction.
Up to 14 BCNT instructions constitute a loop and are repeatedly executed N-2 times. Hereinafter, the value of the current floating point register window pointer in the loop is defined as w. I-th
Let's look at the first loop. As can be seen from the values of the general-purpose registers 1 and 2, The data added by the 10 FADD instructions are A (i) and B (i).
No. 8, no. The data loaded to the physical floating point registers <w + 1, 12> and <w + 1, 13> by the FLDPRM instruction No. 9 are A (i + 1) and B (i + 1), respectively. As can be seen from the value of general-purpose register 3, No. The value of the physical floating-point register <w-1, 20> is C
It is stored in the main storage location of (i-1). No. 12 A
DD instruction and No. The current floating-point register window pointer w is incremented by 1 by the 13 CFRWPS instruction, and the process returns to the top of the loop. That is, in one loop, data A (i + 1) and B (i +
1) respectively correspond to the physical floating-point registers <w + 1, 1
2> and stored in the physical floating-point registers <w + 1, 13>, and the physical loop-point registers <
w, 12> and A (i) and B (i) stored in the physical floating-point register <w, 13>, and the result is stored in the physical floating-point register <w, 20>. A (i) stored in the physical floating-point register <w−1, 20>
-1) + B (i-1) is stored in the main storage location of C (i-1).

No. after exiting the loop. No. 15 to No.
The instruction of No. 19 is processing of an unprocessed element. Fifteen
A (N) + B (N) is executed by the FADD instruction of
16, No. A in each of 19 FSTPOM instructions
(N-1) + B (N-1) and A (N) + B (N) are stored in the main memory.

As can be seen from the processing in the loop, N
o. 8, no. The FLPRM instruction No. 9 specifies the logical floating-point registers 12 and 13 and the immediately following No. 9 10 F
Although the logical floating point registers 12 and 13 are used in the ADD instruction, the physical floating point registers accessed are different. In addition, No. The addition result is stored in the logical floating-point register 20 by the FADD instruction No. 10 and the FSTP
Although the logical floating point register 20 is used in the OM instruction, the physical floating point register accessed is different. Therefore, the phenomenon of waiting for the data reading and the completion of the operation and waiting for the execution of the subsequent instruction which occurred in the program of Table 1 does not occur. In other words, the data is read and the operation is executed in the next loop. That is, the program is executed at high speed. Further, since only three logical floating point registers are specified in the program, there is no need to use many floating point registers as in the program of Table 2.

Here, the program of Table 3 has a process of updating the current floating point register window pointer which is not included in the programs of Tables 1 and 2, and thus has an overhead. For example, while the loop of the program in Table 1 is composed of five instructions, the loop of the program in Table 3 is composed of seven instructions. However, the overhead of waiting for reading of data and waiting for completion of operation in the program of Table 1 and waiting for execution of a subsequent instruction is much larger. Also, the loop unrolling method as shown in the program of Table 2 cannot be realized if the registers that can be specified by the program are exhausted. Therefore, even if there is overhead for updating the current floating-point register window pointer, this method is not applicable. It is believed that the inventive scheme is superior.

As described above, according to the method of the present invention, in the vector calculation of the scientific and technical calculation in which the loop of the instruction sequence is mainly performed, the current floating-point register window pointer is changed for each loop. The window to be used is changed, and the processing of the i-th element is performed by loading the i-th element of the operand vector by the floating-point register preload instruction in the (i-1) -th loop, performing the operation in the i-th loop,
An instruction sequence of load, operation, and store processing for one data is performed by storing the operation result in the i-th element of the result storage vector by the floating-point register post-store instruction in the (i + 1) -th loop. The above distance is increased, and the performance can be prevented from deteriorating due to the influence of the data reading time and the operation execution time, and the speed can be increased.

[0059]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows a data processing apparatus according to the present embodiment. The data processing device includes an instruction processing unit 10 for issuing and executing instructions, a main memory 30 for storing instructions and data to be executed by the instruction processing unit, and data between the instruction processing unit and the main memory. And a storage control unit 20 for controlling the exchange of data.

The instruction processing unit 10 includes an instruction register 101 for holding an instruction to be executed, an instruction control unit 10 for decoding the contents of the instruction register 101 and controlling the instruction execution.
2. A general-purpose register group 103 for holding data required for general-purpose operation and address calculation, a general-purpose arithmetic unit 104 for executing general-purpose operation specified by an instruction, and a physical floating unit for holding data required for floating-point operation. A decimal point register group 105, a floating-point arithmetic unit 106 for executing a floating-point operation specified by an instruction, an address adder 107 for calculating a main storage address for accessing main storage data, and a read from the storage control unit 20. A cache 108 for holding the main memory data, a main memory access control unit 109 for performing control such as reading the main memory data from the storage control unit 20 in accordance with a search result of the cache 108, a current floating point register window pointer Floating point window pointer register 110 for storing the current floating point The current floating-point window pointer valid register 111 indicating that the counter is valid, and the conversion logic 112 for converting the logical floating-point register number specified by the instruction into the physical floating-point register number according to the equations (2) to (6). Be composed.

Here, as shown in FIG. 3, four new instructions are added to the data processing device. They are: (a) a current floating point register window pointer change instruction, (b) a floating point register preload instruction,
(C) an extended floating-point register preload instruction, (d)
Floating point register post store instruction. The current floating point register window pointer change instruction is an instruction for changing the current floating point register window pointer.
The instruction mnemonics and functions of the instructions (a), (b), and (d) are described in the section of “action”. In FIG. 3A, the instruction code indicates that the instruction is a current floating-point register window pointer change instruction. The general-purpose register number designates a general-purpose register in which the value of the current floating-point register window pointer to be set is stored. The floating-point register preload instruction stores the main memory data.
This is an instruction to be stored in the floating-point register belonging to the window of (current floating-point register window pointer + 1). In FIG. 3B, the instruction code indicates that it is a floating-point register preload instruction. The floating-point register number is a logical floating-point register number (referred to as r) in which main memory data is stored, and the corresponding physical floating-point register number is <w + 1, r, where w is the current floating-point register window pointer. >. The value of the general-purpose register is a main memory address for reading data from the main memory. After the reading, the value added to the general-purpose register is the increment value. The extended floating-point register preload instruction is an instruction for storing main storage data in a floating-point register belonging to the window of (current floating-point register window pointer + 2).
In FIG. 3C, the instruction code indicates an extended floating-point register preload instruction. The floating-point register number is a logical floating-point register number (r) in which main storage data is stored, and the corresponding physical floating-point register number is <w + 2, r, where w is the current floating-point register window pointer. >. The value of the general-purpose register is a main memory address for reading data from the main memory. After the reading, the value added to the general-purpose register is the increment value. Although the function of the extended floating-point register preload instruction is not shown in the section of "Operation", it is merely an extension of the extended floating-point register preload instruction and is obvious from the above description. The floating-point register post-store instruction is an instruction to store data from the floating-point register belonging to the window of (current floating-point register window pointer-1) in the main memory. In FIG. 3D, the instruction code indicates that the instruction is a floating-point register post-store instruction. The floating-point register number is the logical floating-point register number (r) from which data is read, and the corresponding physical floating-point register number is <w−1, where w is the current floating-point register window pointer. r>. The value of the general-purpose register is the address of the main memory where the data is stored. After the reading, the value added to the general-purpose register is the increment value. The operation of these instructions will be described with reference to FIG. First, the current floating-point register window pointer change instruction will be described. Instruction register 10
When the instruction is loaded into the instruction control unit 10
When the instruction is decoded in step 2 and it is identified that the instruction is the current floating-point register window pointer change instruction, the general-purpose registers specified in the instruction are read out from the general-purpose register group 103, and the value stored in the register is read out. Set in floating point window pointer register 110.

Next, the floating point register preload instruction will be described. When the instruction is loaded into the instruction register 101, the instruction is decoded by the instruction control unit 102. When the instruction is identified as a floating-point register preload instruction, the address adder 107 operates the general-purpose register designated by the instruction. The content of the general-purpose register indicated by the number is used as a main storage address for reading data from the main storage. The main memory access control unit 109 searches the cache 108 based on the main memory address. If desired data is found in the cache, the data is transferred from the cache. The data is transferred from the main memory 30. The transfer data is stored in the floating-point register 105. The physical floating-point register number of the stored floating-point register is obtained by the conversion circuit 112 as follows. The floating-point register number specified in the instruction is a logical floating-point register number (r), and the value of the current floating-point register window pointer register 110 is w, and <w + 1, r> is a physical floating-point register number. Become. After the start of the data transfer operation, the general-purpose arithmetic unit 104 adds an increment value to the value of the general-purpose register.

Next, the extended floating point register preload instruction will be described. When the instruction is taken into the instruction register 101, the instruction is decoded by the instruction control unit 102,
When it is determined that the instruction is an extended floating-point register preload instruction, the address adder 107 reads the contents of the general-purpose register indicated by the general-purpose register number specified in the instruction from the main memory. The storage address. The main memory access control unit 109 searches the cache 108 based on the main memory address. If desired data is found in the cache, the data is transferred from the cache. The data is transferred from the main memory 30. The transfer data is stored in the floating point register 105. The physical floating point register number of the stored register is obtained by the conversion circuit 112 as follows. The floating-point register number specified in the instruction is a logical floating-point register number (r), and the value of the current floating-point register window pointer register 110 is w, and <w + 2, r> is a physical floating-point register number. Become. After the start of the data transfer operation, the general-purpose arithmetic unit 104 adds an increment value to the value of the general-purpose register.

Next, the floating-point register post-store instruction will be described. When the instruction is loaded into the instruction register 101, the instruction is decoded by the instruction control unit 102, and when the instruction is identified as a floating-point register post-store instruction, the address adder 107 causes the general-purpose register designated by the instruction to operate. The contents of the general-purpose register indicated by the number are used as a main memory address for storing data in the main memory. Data is read from the floating-point register 105. The physical floating-point register number of the register to be read is:
It is obtained by the conversion circuit 112 as follows. The floating point register number specified in the instruction is a logical floating point register number (r), and the value of the current floating point register window pointer register 110 is w,
<W-1, r> is the physical floating-point register number.
The main memory access control unit 109 searches the cache 108 based on the main memory address, and if there is a copy of the data stored in the main memory address of the main memory 30 in the cache, the data is retrieved. If the data is not replaced with the read data, the cache is not operated. Further, the main memory access control unit 109 stores the read data at the main memory address of the main memory 30 via the storage control unit 20. After the start of the data transfer operation, the general-purpose arithmetic unit 104 adds an increment value to the value of the general-purpose register.

Further, general floating-point instructions (operation instructions,
Load instruction, store instruction), the logical floating-point register number r indicated in the instruction is determined by setting the value of the current floating-point register window pointer register 110 to w.
The conversion logic 112 converts the data into a physical floating-point register number represented by w, r>, and refers to the floating-point register indicated by the physical floating-point register number.

When the value of the current floating point window pointer valid register 111 is “1”, the current floating point register window pointer is valid. That is,
Conversion of the logical register number to the physical register number in the conversion circuit 112 is performed. If the conversion result is "0", the conversion of the logical register number to the physical register number is not performed, and the logical floating point register number specified by the instruction remains unchanged. It becomes a register number, and refers to the physical floating point register indicated by the physical floating point register number. Here, the current floating-point window pointer valid register 1
An empty bit of an existing register for storing control information of the data processing system may be assigned to 11, and a value is set using an existing instruction for storing a value in the register.

As described above, the current floating-point register window pointer change instruction, floating-point register preload instruction, extended floating-point register preload instruction, floating-point register post-store instruction, and general control under the control of the current floating-point window pointer Floating point instructions work.

According to the above embodiment, a program as shown in Table 3 can be realized, and the speed of the vector calculation is increased.
It was mentioned in the column of "action".

Therefore, according to the method of the present invention, by changing the current floating-point window pointer, one floating-point register number in an instruction is converted to a different physical floating-point register number. More physical registers than the number can be accessed without changing the architecture of the data processing device, the program as shown in Table 3 can be realized, data is read out, and the execution of the instruction is delayed due to the collision of the registers. Performance can be prevented from being reduced, and high-speed execution of the program is possible.

In particular, as can be seen from the program shown in Table 3, in the vector calculation of the scientific and technical calculation in which the loop of the instruction sequence is mainly performed, the window used for each loop is changed, and the processing of the i-th element is performed. Is the load of the i-th element of the operand vector by the floating-point preload instruction in the (i-1) -th loop, the operation in the i-th loop, the (i + 1) -th loop
By storing the operation result in the i-th element of the result storage vector by the floating-point post-store instruction in the loop, load, operation, and store processing of one data on the instruction sequence is performed. The distance is increased, and the performance can be prevented from deteriorating due to the influence of the data reading time and the operation execution time, and the speed can be increased.

Here, an extended floating-point preload instruction not shown in Table 3 is introduced in the embodiment. This is because, in a system in which the time for reading data from the main memory is long, the program shown in Table 3 is used. When the data loaded in the next loop of the loop that issued the preload instruction is to be calculated, the load has not yet been completed, and the operation instruction waits. May occur. Therefore,
An extended floating point preload instruction has been devised so that it can be programmed to operate on data loaded in the next loop following the loop that issued the preload instruction.

[0072]

According to the present invention, by changing the current floating point window pointer, one floating point register number in an instruction is converted to a different physical floating point register number, so that the number of registers addressable by the instruction Since more physical registers can be accessed without changing the architecture of the data processing device,
It is possible to prevent a decrease in performance due to waiting for instruction execution due to data reading and register collision, and the program can be executed at high speed.

In particular, in the vector calculation of scientific and technical calculation in which the repetition of the loop of the instruction sequence is the main, the window used for each loop is changed, and the processing of the i-th element is performed by the i-1 th element.
Load the i-th element of the operand vector by the floating-point preload instruction in the loop, perform the operation in the i-th loop, and the i-th element of the result storage vector by the floating-point poststore instruction in the (i + 1) -th loop Storing the operation result in the instruction column increases the distance of the load, operation, and store processing for one data on the instruction sequence, and influences the data read time and the operation execution time. Performance can be prevented and the speed can be increased.

[Brief description of the drawings]

FIG. 1 shows a logical floating-point register number according to the present invention.
One embodiment of physical floating point register number conversion.

FIG. 2 is a configuration diagram showing one embodiment of a data processing device for executing the instruction shown in FIG. 3 according to the present invention.

FIG. 3 is a diagram showing an embodiment of a current floating-point register window pointer change instruction, floating-point register preload instruction, extended floating-point register preload instruction, and floating-point register point store instruction according to the present invention.

[Explanation of symbols]

10 is an instruction processing unit, 20 is a storage control unit, 3
0 is a main memory, 101 is an instruction register, 102 is an instruction control unit, 103 is a general-purpose register group, 104 is a general-purpose arithmetic unit, 1
05 is a physical floating-point register group, 106 is a floating-point arithmetic unit, 107 is an address adder, 108 is a cache, 109 is a main memory access control unit, 110 is a current floating-point window pointer register, and 111 is a current floating-point window pointer valid. Register, 112 is conversion logic

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kisaburo Nakazawa 6-29-10 Sagamidai, Sagamihara City, Kanagawa Prefecture (72) Inventor Hiroshi Nakamura 4-1043, Namiki, Tsukuba City, Ibaraki Prefecture (72) Inventor Hiromitsu Hiromitsu Ibaraki 2-23-6, Akubo, Tsukuba, Japan (72) Inventor Hideo Wada 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Hitachi, Ltd. Kanagawa Plant (56) References JP-A-62-98434 Japanese Patent Laid-Open No. 1-161477 (JP, A) Japanese Patent Application Laid-Open No. Sho 62-17873 (JP, A) Japanese Patent Application Laid-Open No. 61-267134 (JP, A) Japanese Patent Application Laid-Open No. 61-241870 (JP, A) Japanese Patent Application Laid-Open No. 61-136131 (Japanese) JP, A) JP-A-60-129838 (JP, A) JP-A-5-233279 (JP, A) Daniel Tabak, translated by Kenji Omori, RISC system, Japan, Kaibundo Publishing Co., Ltd., November 1991 Day, first edition, p. 110-116 D.C. R. Miller, D.M. J. Quammen, Exploiting large register sets, Microprocessors and Microsystems, Butterworth-Hein emann Ltd., UK. , 1990, Vol. 14, No. 6, p. 333-340 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 17/16 G06F 9/30-9/355 G06F 9/38 G06F 9/40-9/42 G06F 9/46-9 / 54

Claims (6)

(57) [Claims] An instruction is executed using a main memory for holding instructions and data, and main memory data held in the main memory.
The instruction includes reading main memory data from the main memory,
Load instruction stored in the register numbered in the instruction
If, de to the main storage from the numbered by the register in the instruction - and the store instruction for storing data, performs calculation, and operation instructions to be stored in the numbered by the register computation results in an instruction <br/> de consisting instruction processing unit comprising - in data processing apparatus, a register called more physical registers than the number of addressable registers by the instruction, from a plurality of bits
Register called window pointer register
When, the transformation and register called 1-bit window pointer valid register, when the value of the window pointer valid register is 1, and converts the register number in the instruction to a physical register number, and the value of the window pointer register Bei and a conversion circuit to change the emissions - of pattern
The instructions executed by the instruction processing unit include a window pointer change instruction for changing the value of the window pointer register, and a register number in the instruction determined from the value of the window pointer register. A register preload instruction which regards a value different from the register value as a value of the window pointer register, converts the value into a physical register number by the conversion circuit, and stores main memory data in the physical register indicated by the physical register number ; The register number in the instruction is determined from the value of the window pointer register, but a value different from the value of the window pointer register is regarded as the value of the window pointer register, and the conversion circuit converts the value into a physical register number. de read from the physical register indicated by the physical register number And a register poststore instruction for storing in the main memory data, said instruction processing unit, said register preload - de instruction, the B excluding the register poststore instruction - de instruction, the store instruction, and execution of the operation instruction In some cases, the register number in the instruction is converted into a physical register number by the conversion circuit using the value of the window pointer register, and the physical register indicated by the physical register number is referred to when executing the register preload instruction.
Indicates the register number in the instruction
Determined from the register value, the window pointer register
The window pointer register to a value different from the
Data is converted to a physical register number by the conversion circuit.
The main memory is stored in the physical register indicated by the physical register number.
Storing data and executing the register post-store instruction
Sometimes, the register number in the instruction is
Window pointer
A value different from the value of the register
Assuming the value of the register
To the physical register indicated by the physical register number.
A data processing device for storing read data in a main memory . 2. The data processing apparatus according to claim 1 , wherein said instruction processing unit uses a value obtained by adding an arbitrary integer to the value of said window pointer register when executing said register preload instruction. Data processing device. 3. The buffer memory device according to claim 1 , wherein said instruction processing unit temporarily stores a part of the contents of said main memory when reading said main memory data when said register preload instruction is executed. If the main memory data is not registered in a certain cache, the contents of the cache are changed .
On the other hand , when the register post-store instruction is executed , if the main memory data of the corresponding main memory address is not registered in the cache in writing the data to the main memory, the content of the cache is changed. 2. The data processing apparatus according to claim 1, wherein the data processing is not changed. 4. A set of said physical register numbers which can be converted from a register number in an instruction by a value of said window pointer register in converting said register number in said instruction to said physical register number; The set of physical register numbers that can be converted from the register number in the instruction by one different value includes one or more identical register numbers called the overlap register number; One or a plurality of the register numbers are converted into the same physical register number called a global register number irrespective of the value of the window pointer register, and other than the overlapping register number and the global register number The physical register number of only one value of the window pointer register De according to claim 1, characterized in that the the outcome converted I - data processing device. 5. The data processing according to claim 1, wherein the registers numbered in the instruction and the physical registers are dedicated registers for storing floating-point numbers, called floating-point registers. apparatus. 6. The instruction processing unit performs an operation of setting a value in the window pointer register or increasing or decreasing the value of the window pointer register when executing the window pointer change instruction. The data processing apparatus according to claim 1, wherein: