JP2875426B2 - Pseudo vector processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly, to a technique for enabling a data processing apparatus to access more registers than the number of registers addressable by an instruction. In particular, in this manner, in the so-called vector processing for continuously processing large-scale data for which the cache is not very effective, the transfer from the main memory is mainly used for the list vector operation mainly used for calculating the sparse matrix. The present invention relates to a technique which makes it possible to realize efficient pseudo vector processing with an ordinary data processing device by preventing almost any performance degradation from occurring.

[0002]

2. Description of the Related Art Conventionally, as a technique for enabling a data processing device to access more registers than the number of registers addressable by an instruction, Japanese Patent Laid-Open No.
According to this method, first, a register group called a hardware register is provided which is larger than the number of general-purpose registers addressable by a program, and a plurality of registers for the same general-purpose register are provided from different main memory addresses. Are stored in the hardware register by the number of the load instructions (that is, the number of the load instructions).
If the number of general-purpose registers that can be addressed by the program is 16, hardware registers are prepared for each general-purpose register, ie, a total of 256 hardware registers.
Hardware registers 0 to 15 are assigned to general-purpose register 0. When a load instruction specifying 16 different main storage addresses is executed for the general-purpose register 0, data from the 16 load instructions is transferred from the hardware register 0 to the hardware register 0. The data is stored in the hardware register 15). A storage mechanism is provided for registering a main memory address of a previously executed load instruction and a hardware register number in which data loaded at that time is stored. If the main memory address of the load instruction matches the main memory address registered in the storage mechanism, the data is not read from the main memory, and the corresponding hardware is read.
Reads data from the hardware register. According to this method, the number of times of referring to the main memory can be reduced, and performance degradation due to collision of the reference register between instructions can be prevented.

(Prior Art 2) Conventionally, as a technique for enabling a data processing device to access more registers than the number of registers addressable by an instruction, J. L. Hen
nesy and D.S. A. Patternson "C
outputArchitecture: A Q
"antiativeApproach", Mor
gan Kaufmann Publish-ers,
Inc. (1990). According to this method, first, a register called a physical register that is larger than the number of registers addressable by a program is provided, and the physical register is divided into a plurality of windows. That is, each window is composed of a plurality of physical registers. For example, assume that registers are numbered from 1 to n by a program, and physical registers are n
* M, that is, numbers 1 to n * m are provided. Assuming that there are m windows, that is, numbers 1 to m, window 1 can be assigned to physical registers 1 to n, window 2 can be assigned to physical registers n + 1 to 2n, and so on. In practice, it is customary to provide a physical register common to all windows and a common physical register adjacent to windows, but for simplicity,
The above example was shown. Each window has registers used by one program. That is, referring to a register that can be addressed by a program is actually
It refers to a physical register belonging to a certain window. For example, in the above example, if window 2 is assigned to a certain program, if register k is specified in the program, the physical register to be referred to is physical register n + k.

This window is used as follows. If window j is assigned to a certain program, the program calls another program (cal
l), the called program contains a window j
+1 is assigned. Further, when a window j is allocated to a certain program, when the program returns (returns) to the program that called the program, the return destination program includes a window j-1.
Is assigned. By using in this way, the following effects are obtained. In a system having only as many registers as the number of registers that can be addressed by a program, each time a program call as described above occurs, the data stored in the register is used to save information at the time of the call. Must be stored in the main memory, and every time the program returns, the data stored in the main memory must be written back to the register in order to restart the program. In a system having the above window mechanism, since a program to which a different window is assigned refers to a different physical register, an operation of storing data from the above-mentioned register to the main memory and writing back from the main memory to the register is performed. Becomes unnecessary, and the processing speed is increased.

[0005] However, in a system having the window mechanism, when a program call is issued from the program having the largest window number, the window overflow is performed.
When the program returns from the program with the smallest window number, a window underflow interrupt is caused. "

[0006]

SUMMARY OF THE INVENTION The present invention relates to a technique for enabling a data processing device to access more registers than the number of registers addressable by an instruction. An example will be described in which a floating-point register storing a floating-point number is described as the first register, and a general-purpose register storing a fixed-point number, logical data, binary integer, and the like is described as the second register.

An important operation in scientific and technical calculations is a list vector operation. It is expressed by the following equation and is mainly used for calculating a sparse matrix.

Source index type operation: A (i) = B (Li (i)) i = 1, N (1) Target index type operation: A (Li (i)) = B (i) i = 1, N (2) Particle propulsion type operation: A (Li (i)) = A (Li (i)) ＠ B (i) i = 1, N (3) Here, Li is called a list vector. In (1),
A and Li are vectors of the number of elements N, and in (2), B and Li
Is a vector of the number of elements N, and in (3), B and Li are vectors of the number of elements N. In (3), ＠ indicates an operation such as addition, subtraction, multiplication and division.

As can be seen from equation (1), the source index type operation is that the element of vector B having the element number of the i-th element of the list vector is stored in the i-th element of vector A. is there. As can be seen from equation (2), in the target index type operation, the ith element of the vector B is stored in the element of the vector A whose element number is the ith element of the list vector. As can be seen from equation (3), the particle propulsion type operation is performed by
The element of the vector A whose element number is the element of the vector B is operated on the ith element of the vector B, and the operation result is stored in the element of the vector A whose element number is the ith element of the list vector. That is, equations (1), (2), and (3)
Is an operation in which the element number of a certain vector is used as an element of another vector (list vector). Here, Equation (3) is often used in the field of particle propulsion among calculations of sparse matrices, and will be referred to as a particle propulsion type operation. Less than,
In this patent, an example will be described in which the operation of equation (3) (that is, ＠) is added.

When the equation (1) is executed by a general-purpose computer, a program as shown in Table 1 is obtained.

[0011]

[Table 1]

In the following description, the data width of a general-purpose register and a floating-point register is assumed to be 8 bytes.

The function of each instruction in Table 1 will be described below.

GLDMa (GRm), GRn (Function) Reads 8 bytes of data from the main memory address represented by the value of general-purpose register m and stores it in general-purpose register n.

Thereafter, the value of the general-purpose register m is added by a.

FLDM a (GRm), FRn (Function) 8-byte data is read from the main memory address represented by the value of the general-purpose register m and stored in the floating-point register n.

Thereafter, the value of the general-purpose register m is added by a.

FSTM a (GRm), FRn (Function) Stores the value (8 bytes) of floating-point register n in the main memory address represented by the value of general-purpose register m.

Thereafter, the value of the general-purpose register m is added by a.

BCNT GRm, t (Function) Decreases the value of general-purpose register m by one. If the value is not zero, branch to address t. If zero, do not branch.

Here, it is assumed that the vector L is stored in a continuous area starting from the main storage address ad1 prior to the execution of the program shown in Table 1. That is, L
The main storage address of (1) is stored as ad1, and the main storage address of L (2) is stored as ad1 + 8. Similarly, the vector A is stored in a continuous area starting from the main storage address ad2. It is assumed that the vector B is stored in a continuous area starting from the main storage address ad3. It is assumed that ad1 is stored in the general-purpose register 1, ad2 is stored in the general-purpose register 2, and N is stored in the general-purpose register 4 in advance. Here, the vector L is obtained by modifying the list vector Li as follows.

L (i) = 8 * (Li (i) −1) + ad3 (4) That is, the address of B (Li (i)) is stored in L (i). When trying to realize Equation (1) using Li (i), an operation of multiplying (Li (i) -1) by 8 and a
Since the operation of adding d3 is inserted and the program becomes complicated, L (i) is introduced for simplification.

As can be seen from Table 1, no. 1 GLD
With the M instruction, L (i) is loaded into the general-purpose register 20,
No. With the FLDM instruction No. 2, B (Li (i)) is loaded into the floating-point register 20 from the main memory address indicated by the general-purpose register. The value of the floating-point register is stored in A (i) by the third FSTM instruction.

That is, by executing a loop consisting of four instructions once, a result of one element is obtained.
By executing the loop N times, all element calculations can be performed.

Here, the execution time of one loop becomes a problem. First, no. The data is loaded from the main memory to the general-purpose register 20 by the GLDM instruction of No. 1. FLD of 2
Since the M instruction uses the general-purpose register 20, the execution cannot be started unless the load is completed. In addition, No. The FLDM instruction No. 2 loads data from the main memory to the floating-point register 20, The third FSTM instruction uses the floating-point register 20, so that the execution cannot be started unless the load is completed. Here, No. 1 GLDM
Instruction and No. Data is loaded from the main memory to the general-purpose register 20 and the floating-point register 20 by the FLDM instruction No. 2; however, if there is data in the cache, the GL is used.
The DM and FLDM instructions end in a short number of cycles, but if they are not in the cache, the data must be read from main memory, which is much slower than the cache. In comparison, it will take much time. That is, (1) data read time,
(2) Two performance degradation factors, such as register collision, increase the execution time of the loop. In particular, the case (1) is serious in the case of calculation for handling long data, and in many cases, necessary data cannot be stored in the cache, resulting in a large decrease in performance.

Similarly, when equation (2) is executed by a general-purpose computer, a program as shown in Table 2 is obtained.

[0027]

[Table 2]

Here, it is assumed that the vector L is stored in a continuous area starting from the main storage address ad1 prior to execution of the program shown in Table 2. That is, L
The main storage address of (1) is stored as ad1, and the main storage address of L (2) is stored as ad1 + 8. Similarly, the vector B is stored in a continuous area starting from the main storage address ad2. It is assumed that the vector A is stored in a continuous area starting from the main storage address ad3. It is assumed that ad1 is stored in the general-purpose register 1, ad2 is stored in the general-purpose register 2, and N is stored in the general-purpose register 4 in advance. Here, the vector L is obtained by modifying the list vector Li as shown in Expression (4).
That is, the address of A (Li (i)) is stored in L (i).

As can be seen from Table 2, 1 GLD
With the M instruction, L (i) is loaded into the general-purpose register 20,
No. B (i) is loaded into the floating-point register 20 by the FLDM instruction No. 2 and the FL. 3, the main memory address indicated by the general-purpose register, that is, A
The value B (i) of the floating-point register is stored at the main storage address of (Li (i)).

That is, by executing a loop consisting of four instructions once, a result of one element is obtained.
By executing the loop N times, all element calculations can be performed.

Here, similarly to Table 1, the execution time of one loop becomes a problem. First, no. Data is loaded from the main memory to the general-purpose register 20 by one GLDM instruction.
o. Since the FSTM instruction of No. 3 uses the general-purpose register 20, the execution cannot be started unless the loading is completed. In addition, No. 2 FLDM instructions are floating point register 2
No. 0 is loaded with data from the main memory. 3 F
Since the STM instruction uses the floating point register 20, the execution cannot be started until the loading is completed. In other words, as in Table 1, two performance degradation factors, (1) data read time and (2) register collision, increase the loop execution time. In particular, the case (1) is serious in the case of a calculation that handles long data, and in many cases, the necessary data cannot be stored in the cache.
The decrease in performance is significant.

Similarly, when equation (3) is executed by a general-purpose computer, a program as shown in Table 3 is obtained. Here, an example of addition is shown as an operation in Expression (3).

[0033]

[Table 3]

The functions of the newly added instructions in Table 3 are shown below.

FADD FRm, FRn (Function) The value (8 bytes) of the floating-point register m and the value (8 bytes) of the floating-point register n are added and stored in the floating-point register m.

Here, it is assumed that the vector L is stored in a continuous area starting from the main storage address ad1 prior to the execution of the program shown in Table 3. That is, L
The main storage address of (1) is stored as ad1, and the main storage address of L (2) is stored as ad1 + 8. Similarly, the vector B is stored in a continuous area starting from the main storage address ad2. It is assumed that the vector A is stored in a continuous area starting from the main storage address ad3. It is assumed that ad1 is stored in the general-purpose register 1, ad2 is stored in the general-purpose register 2, and N is stored in the general-purpose register 4 in advance. Here, the vector L is obtained by modifying the list vector Li as shown in Expression (4).
That is, the address of A (Li (i)) is stored in L (i).

As can be seen from Table 3, no. 1 GLD
With the M instruction, L (i) is loaded into the general-purpose register 20,
No. B (i) is loaded into the floating-point register 21 by the FLDM instruction No. 2 and 3 FLDM instruction, the main memory address indicated by the general-purpose register, that is, A
A (Li (i)) from the main memory address of (Li (i))
Is read out and stored in the floating-point register 20.
No. 4, the value of the floating-point register 20 (that is, A (Li (i))) and the value of the floating-point register 21 (that is, B (i)) are added, and stored in the floating-point register 20. No. 5, the value of the floating-point register 20 (that is, A (Li
(I)) + B (i)) is stored in the main storage address indicated by the general-purpose register, that is, the main storage address of A (Li (i)).

That is, by executing a loop consisting of six instructions once, a one-element result is obtained.
By executing the loop N times, all element calculations can be performed.

Here, similarly to Table 1, the execution time of one loop becomes a problem. First, no. Data is loaded from the main memory to the general-purpose register 20 by one GLDM instruction.
o. Since the FLDM instruction No. 3 uses the general-purpose register 20, the execution cannot be started unless the loading is completed. In addition, No. 2 FLDM instructions are floating point register 2
No. 1 loads data from the main memory. F of 4
Since the ADD instruction uses the floating-point register 21, execution cannot be started unless the loading is completed. Also, N
o. The FLDM instruction of No. 3 loads data from the main memory to the floating-point register 20, and Since the FADD instruction No. 4 uses the floating-point register 20, the execution cannot be started until the loading is completed. In addition, No. The FADD instruction No. 4 stores the result of the operation in the floating-point register 2
0 and stored in No. Since the FSTM instruction No. 5 uses the floating-point register 20, it cannot be executed unless the operation and storage are completed. In other words, as in Table 1, two performance degradation factors, (1) data read time and (2) register collision, increase the loop execution time. In particular, the case (1) is serious in the case of calculation for handling long data, and in many cases, necessary data cannot be stored in the cache, resulting in a large decrease in performance.

One method for solving the two problems of performance degradation, namely, (1) data read time and (2) register collision, which occurs in the programs shown in Tables 1, 2 and 3, is a loop unrolling method. It is a ring.
Table 4 shows the result of applying the Pun rolling method.
Table 5 shows an example in which the loop unrolling method is applied to the program in Table 2, and Table 6 shows an example in which the loop unrolling method is applied to the program in Table 3. That is, a plurality of elements (= n) are processed in one loop, and the number of loops is reduced by 1 / compared to the case where one element is processed in one loop.
This is a method of setting n. Table 4, Table 5, and Table 6 are all systems for processing four elements in one loop.

[0041]

[Table 4]

[0042]

[Table 5]

[0043]

[Table 6]

First, Table 4 will be described. Here, it is assumed that prior to the execution of the program in Table 4, the vector L is stored in a continuous area starting from the main storage address ad1. That is, the main storage address of L (1) is a
The main storage addresses of d1 and L (2) are stored as ad1 + 8. Similarly, the vector A is stored in a continuous area starting from the main storage address ad2.
It is assumed that the vector B is stored in a continuous area starting from the main storage address ad3. General-purpose register 1
Is stored in advance, ad2 is stored in general-purpose register 2, and N / 4 is stored in general-purpose register 4 in advance. Here, the vector L is obtained by modifying the list vector Li as shown in Expression (4).

As can be seen from Table 4, by executing a loop consisting of 13 instructions once, a four-element result is obtained, and by executing this loop N / 4 times, the calculation of all elements is completed. it can.

As can be seen from Table 4, with respect to the i-th element, the load of L is changed to No. With one GLDM instruction, B (L
The load of i) is No. 5 FLDM instruction, B (Li)
Is stored in A. 9 with the FSTM instruction. Similarly, regarding the (i + 1) th element, the load of L is set to No. The GLDM instruction of No. 2 changes the load of B (Li) to No. FL of 6
With the DM instruction, the storage of B (Li) in A is No. 10 F
This is performed by the STM instruction. Similarly, for the i + 2 element,
L is No.L. The GLDM instruction of No. 3 changes the load of B (Li) to No. 3. In the FLDM instruction of No. 7, the storage of B (Li) in A is No. 11 FSTM instructions. Similarly, i
With respect to the + 3rd element, the load of L is No. 4 GLD
With the M instruction, the load of B (Li) is set to No. No. 8, the storage of B (Li) in A is No. 12 FSTM
Perform by instruction. Therefore, as compared with Table 1, a series of processing of loading an L element, loading a B (Li) element, and storing a B (Li) element in A corresponding to a certain element number. Are separated on the instruction sequence, and the above-mentioned (1) data read time and (2) register collision occur.
The effect of the two performance degradation factors can be reduced. For example, N
o. With one GLDM instruction, L (i) is loaded,
Since the load result is used after 4 instructions,
If the data reading time is within 4 cycles,
No. to use the result 5 FLDM instructions are not awaited. In addition, No. The B (Li (i)) loaded by the FLDM instruction of No. 5 is used after four instructions, so if the data read time is within four cycles, the load result is used. . Nine FSTM instructions are not awaited.

Next, Table 5 will be described. Here, it is assumed that the vector L is stored in a continuous area starting from the main storage address ad1 prior to execution of the program in Table 5. That is, the main storage address of L (1) is a
The main storage addresses of d1 and L (2) are stored as ad1 + 8. Similarly, the vector B is stored in a continuous area starting from the main storage address ad2.
It is assumed that the vector A is stored in a continuous area starting from the main storage address ad3. General-purpose register 1
Is stored in advance, ad2 is stored in general-purpose register 2, and N / 4 is stored in general-purpose register 4 in advance. Here, the vector L is obtained by modifying the list vector Li as shown in Expression (4).

As can be seen from Table 5, by executing a loop consisting of 13 instructions once, a four-element result is obtained, and by executing this loop N / 4 times, the calculation of all elements becomes it can.

As can be seen from Table 5, the load of L is set to No. With one GLDM instruction, B
No. to No. In the FLDM instruction of No. 5, the storage of B in A (Li) is No. 9 with the FSTM instruction. Similarly, regarding the (i + 1) th element, the load of L is set to No. The GLDM instruction of No. 2 changes the load of B to No. 6 FLDM instructions, B's A
(Li) is stored in No. Performed by 10 FSTM instructions.
Similarly, regarding the (i + 2) th element, the load of L is changed to No.
In the GLDM instruction of No. 3, the load of B is No. 7 FLDM
With the instruction, the storage of B in A (Li) is No. 11 FSTs
Perform with M instructions. Similarly, regarding the (i + 3) th element, the load of L is set to No. 4 GLDM instruction, load B to N
o. The FLDM instruction of 8 stores B in A (Li) by N
o. 12 FSTM instructions. Therefore, compared to Table 2, the row of the element of L corresponding to a certain element number
A series of processes, ie, loading of the element of B, loading of the element of B, and storing of the element of B in A (Li) are separated on the instruction sequence. 2.) It is possible to reduce the influence of two performance degradation factors, such as register collision.
For example, No. With one GLDM instruction, the row of L (i)
Since the load result is used and the load result is used after eight instructions, if the data read time is within eight cycles, No. using the load result is used. Nine FSTM instructions are not awaited. In addition, No. Since B (i) loaded by the FLDM instruction of No. 5 is used after four instructions, if the data read time is within four cycles, No. 5 using the load result is used. Nine FSTM instructions are not awaited.

Next, Table 6 will be described.

Here, it is assumed that the vector L is stored in a continuous area starting from the main storage address ad1 prior to the execution of the program shown in Table 6. That is, L
The main storage address of (1) is stored as ad1, and the main storage address of L (2) is stored as ad1 + 8. Similarly, the vector B is stored in a continuous area starting from the main storage address ad2. It is assumed that the vector A is stored in a continuous area starting from the main storage address ad3. It is assumed that ad1 is stored in general-purpose register 1, ad2 is stored in general-purpose register 2, and N / 4 is stored in general-purpose register 4 in advance. Here, the vector L is obtained by modifying the list vector Li as shown in Expression (4).

As can be seen from Table 6, by executing the loop consisting of 21 instructions once, a four-element result is obtained. By executing this loop N / 4 times, the calculation of all elements is completed. it can.

As can be seen from Table 6, the load of L is set to No. With one GLDM instruction, B
No. to No. 5, the load of A (Li) is set to No. 9 FLDM instructions add B and A (Li) to N
o. No. 13 indicates that the addition result is stored in A (Li) by the FADD instruction No. 13. 17 FSTM instructions. Similarly, i +
Regarding the first element, the load of L is No. GLDM of 2
Instruct the load of B to No. 6 FLDM instructions, A
The load of (Li) is No. In the FLDM instruction of No. 10, the addition of B and A (Li) is No. In the FADD instruction No. 14, the storage of the addition result in A (Li) is No. 18 FSTM instructions. Similarly, regarding the (i + 2) th element, the load of L is changed to No. In the GLDM instruction of No. 3, the load of B is No. 7, the load of A (Li) is set to No. 7 by the FLDM instruction of No. 7. 11 F
In the LDM instruction, the addition of B and A (Li) is No. 15 F
With the ADD instruction, the storage of the addition result in A (Li) is No.
19 FSTM instructions. Similarly, regarding the (i + 3) th element, the load of L is set to No. In the GLDM instruction of No. 4, the load of B is No. 8 FLDM instruction, A (Li)
No. to No. In the FLDM instruction No. 12, the addition of B and A (Li) is No. With 16 FADD instructions, A (L
i) is stored in No. 20 FSTM instructions. Therefore, as compared with Table 3, one element number corresponds to
Load of L element, load of B element, load of A (Li) element, addition of B element and A (Li) element, storage of addition result in A (Li) The series of processes described above are separated on the instruction sequence, and the effects of the two performance degradation factors (1) data read time and (2) register collision can be reduced. For example, No. 1 GLD
The L (i) is loaded by the M instruction, and the result of the load is used after 8 instructions. If the data read time is within 8 cycles, the load is performed. Use result N
o. Nine FLDM instructions are not awaited. Also,
No. Since B (i) loaded by the FLDM instruction of No. 5 is used after eight instructions, if the data read time is within eight cycles, the No. 5 using the load result is used. 1
No 3 FADD instruction is awaited. Also, N
o. 13, the operation result stored in the floating-point register by the FADD instruction, that is, A (Li (i)) + B
Since (i) is used after four instructions, if the time required for the operation and storing the operation result is within four cycles, N
o. Seventeen FSTM instructions are not awaited.

Thus, while loop unrolling improves performance, the disadvantage of this scheme is that it requires many registers. The program in Table 1 requires one floating-point register and one general-purpose register for storing vector data, while the program in Table 4 uses four floating-point registers and four general-purpose registers. I need. Similarly, the program in Table 2 is a vector data
The program in Table 5 requires four floating point registers and four general registers, while one floating point register and one general purpose register are required for data storage. Similarly, the program in Table 3 requires two floating point registers and one general purpose register for storing vector data, while the program in Table 6 requires eight floating point registers and four general purpose registers. Requires general purpose registers. Date
If the time required to read the data is longer or the time required for the operation is longer, more elements must be processed in one loop, and more registers are required. Become.

In general, a register is made up of active elements (ie, not memory elements),
Port for writing (ie, data entry / exit)
Can be prepared, so that the speed of the storage device is much higher than that of a storage device which can only read / write one piece of data in one operation cycle. Therefore, it is indispensable to have a register with a sufficient capacity for speeding up, not only the main memory but also the cache. Nevertheless, conventionally, the number of registers was relatively small because of the high cost per bit and the restriction on the length of the register number field in the instruction format as shown below. Because there was. Although the problem of cost is being solved by LSI,
The latter was still unresolved.

However, the number of registers that can be addressed by a program is limited in terms of architecture. For example, if the instruction word has a register specification field of 5 bits, the number of addressable registers is 32 (5 of 2).
Squared). Increasing the number of bits in the register specification field increases the number of registers that can be addressed by the program, but changes the instruction format, and requires modification of the existing program, which is impractical.

Therefore, it is necessary to provide a method that allows the data processing device to access more registers than the number of registers addressable by an instruction without changing the architecture of the data processing device. In 1, when a new load instruction is issued for a main memory address where a load instruction was executed in the past, the speed is increased. However, in many cases, the vector calculation as in the equations (1), (2), and (3) is performed only once when a load request for one main memory address is issued as in the programs shown in Tables 1, 2, and 3. Therefore, there is a problem that the speed is not increased by the conventional technology.

Further, in the prior art 2, only one physical register belonging to a certain window can be used in one program, and the number thereof is equal to the number of registers addressable by the program, and the number of operations performed by one program Can not speed up. In other words, the function of the window can be speeded up only when a program call and return occur, and the processing can be performed by one program as in the vector calculation of equations (1), (2) and (3). There is a problem that the speed is not increased when the operation is completed. Also,
The interruption of the window overflow and the window underflow is completed by one program as in the vector calculation of the equations (1), (2) and (3). If it does not occur, there is a problem that it is unnecessary.

An object of the present invention is to make it possible for a data processing device to access more registers than the number of registers addressable by an instruction without changing the architecture of the data processing device, and to provide a list for scientific and technical calculations. An object of the present invention is to provide a method for performing vector calculation at high speed.

[0060]

In order to achieve the above object, a floating point register called a physical floating point register, called a logical floating point register number, which has more than the number of floating point registers addressable by an instruction,
A current floating-point window pointer register for storing a current floating-point window pointer indicating a pattern for converting a floating-point register number in a program instruction into a physical floating-point register number, a logical floating-point register using the current floating-point window pointer A first conversion circuit for converting a number into a physical floating-point register number, a general-purpose register called a physical general-purpose register having more than the number of floating-point registers addressable by an instruction and the number of general-purpose registers addressable by an instruction, and the logical floating-point register A current general-purpose window pointer register, a current general-purpose window that stores a general-purpose window pointer indicating a pattern for converting a general-purpose register number in a program instruction into a physical general-purpose register number, which is called a number or a logical general-purpose register number. A second conversion circuit for converting the logical floating-point register number or the logical general-purpose register number into a physical general-purpose register number by using a pointer, a current floating-point window pointer, and a value indicating that the current general-purpose window pointer is valid. The current window pointer valid register, the current floating point window pointer change instruction for setting the current floating point window pointer, the current general purpose window pointer change instruction for setting the current general purpose window pointer, and the logical general purpose register number are converted using the current general purpose window pointer. Data is read from the main memory address stored in the physical general-purpose register, and the logical floating-point register number is determined from the current floating-point window pointer, but a value different from the current floating-point window pointer is determined. A floating-point register preload instruction for storing the data and a logical floating-point register number are determined from the current floating-point window pointer in the physical floating-point register converted as the doe pointer, but a value different from the current floating-point window pointer Is read from the physical floating-point register converted as a current floating-point window pointer, and the logical general-purpose register number is stored in the main memory address stored in the physical general-purpose register converted using the current general-purpose window pointer. Floating-point register post-store instruction for storing data, the register number in the instruction is determined from the current general-purpose window pointer, but a value different from the value of the current general-purpose window pointer is converted into the physical general-purpose register as the current general-purpose window pointer. Main memory address stored The logical floating-point register number is determined from the current floating-point window pointer, but a value different from the current floating-point window pointer value is converted to a physical floating-point register converted as the current floating-point window pointer value. A floating-point register list load instruction for storing the data, and a main register using the information stored in the physical general-purpose register obtained by converting the first logical general-purpose register number using the value of the current general-purpose window pointer. The storage address is determined, data is read from the main storage address, and the second logical general-purpose register number is determined from the current general-purpose window pointer, but a value different from the current general-purpose window pointer is used as the current general-purpose window pointer. General register list load instruction to store in converted physical general register, logical floating point The data is read from the physical floating-point register in which the register number is determined from the current floating-point window pointer but is different from the value of the current floating-point window pointer as the value of the current floating-point window pointer, and the register in the instruction is read. The number is determined from the current general-purpose window pointer, but the data is stored in the main memory address stored in the physical general-purpose register obtained by converting a value different from the value of the current general-purpose window pointer as the current general-purpose window pointer. Provide a floating point register list store instruction.

The "register number in the instruction" in the above description of the floating point register reload instruction is a logical floating point register number or a logical general purpose register number. Indicates the decimal point register number. The operation of "determining the main storage address using the information stored in the physical general-purpose register" in the description of the above general-purpose register list load instruction is performed by directly using the information stored in the physical general-purpose register. The storage address will be described in the embodiment. The “register number in the instruction” in the above description of the floating-point register list store instruction is a logical floating-point register number or a logical general-purpose register number, but the embodiment shows the logical floating-point register number. .

[0062]

The floating-point registers other than the floating-point register preload instruction, the floating-point register post-store instruction, the floating-point register list-load instruction, the general-purpose register list-load instruction, and the floating-point register list-store instruction. If the value of the current window pointer valid register is 1, the logical floating-point register number-physical floating-point register number conversion is performed using the value of the current floating-point window pointer. The reference refers to the physical floating-point register number. If the value of the current window pointer valid register is 0, the logical floating point register number is equal to the physical floating point register number. Instructions for referring to general-purpose registers other than the floating-point register preload instruction, the floating-point register post-store instruction, the floating-point register list load instruction, the general-purpose register list load instruction, and the floating-point register list store instruction In all cases, if the value of the current window pointer valid register is 1, the logical general-purpose register number-physical general-purpose register number conversion is performed using the current general-purpose window pointer, and the physical general-purpose register number is referred to by referring to the general-purpose register. . If the value of the current window pointer valid register is 0, the logical general register number is equal to the physical general register number.

The floating-point register preload instruction,
In the floating-point register post-store instruction, the floating-point register list-load instruction, the general-purpose register list-load instruction, and the floating-point register list-store instruction, if the value of the current window pointer valid register is 1, According to the instruction specifications, logical floating-point register number-physical floating-point register number conversion, logical floating-point register number-physical general-purpose register number conversion, logical general-purpose register number-physical general-purpose register number conversion are performed,
The physical floating-point register or the physical general-purpose register indicated by the converted number is referred to. If the value of the current window pointer valid register is 0, the logical floating-point register number is equal to the referenced physical floating-point register number with respect to the logical floating-point register number-physical floating-point register number conversion in the above-mentioned instruction specification. For the logical floating-point register number-physical general-purpose register number conversion, the logical floating-point register number is equal to the referenced physical general-purpose register number, and for the logical general-purpose register number-physical general-purpose register number conversion, the logical general-purpose register number is referred to. Equivalent to the physical general register number.

The conversion of the logical floating-point register number to the physical floating-point register number is performed as follows. A plurality of ranges of the logical floating-point register number that specify the physical floating-point register number are provided, and the specification of this range is called a window.

FIG. 1 shows an example of how to provide a window. In this example, there are 32 logical floating point registers, and logical floating point register numbers 0 to 31 can be specified. There are 88 physical floating point registers, and physical floating point register numbers are 0 to 87. The window is w
0 to w3 are provided and specified by the current floating point window pointers 0 to 3, respectively.

Here, the current floating point window pointer is represented by w, the logical floating point register number is represented by r, and the physical floating point register number is determined by w and r.
w, r>.

An instruction is used to increase or decrease w, and the increase or decrease is performed modulo 4. For example, when w = 3, the value of w + 1 is 0.

In the example of FIG. 1, the conversion of the logical floating point register number to the physical floating point register number is performed as follows.

1. When 0 ≦ r ≦ 7: <w, r> = r regardless of w (5) When 8 ≦ r ≦ 31: <0, r> = r (6) <1, r> = r + 20 (7) <2, r> = r + 40 (8) <3, r> = r + 60 (8 ≦ r ≦ 27) r-20 (28 ≦ r ≦ 31) (9) Logical floating-point register number-physical general-purpose register number conversion and logical general-purpose register number-physical general-purpose register number conversion are performed as follows. A plurality of ranges of the logical floating-point register number and the logical general-purpose register number that specify the physical general-purpose register number are provided, and the specification of this range is called a window.

FIG. 2 shows an example of how to provide a window. In this example, the number of logical floating-point registers is 32, the number of logical floating-point registers can be specified from 0 to 31, and the number of logical general-purpose registers is 32, and the number of logical general-purpose registers can be specified from 0 to 31. The number of physical general-purpose registers is 88, and the number of physical general-purpose registers is 0 to 87. The windows are provided in four ways, wG0 to wG3, and are specified by current general-purpose window pointers 0 to 3, respectively.

Here, the current general-purpose window pointer is set to w
G, the logical floating-point register number or the logical general-purpose register number is denoted by r, and the physical general-purpose register numbers are wG and r.
Therefore, it is described as <wG, r>.

The value of wG is increased or decreased by an instruction.
Is performed modulo. For example, if wG = 3, wG
The value of +1 becomes 0.

In the example of FIG. 2, the conversion of the logical floating-point register number or the logical general-purpose register number to the physical general-purpose register number is performed as follows.

1. When 0 ≦ r ≦ 7: <wG, r> = r regardless of wG (10) When 8 ≦ r ≦ 31: <0, r> = r (11) <1, r> = r + 20 (12) <2, r> = r + 40 (13) <3, r> = r + 60 (8 ≦ r ≦ 27) r-20 (28 ≦ r ≦ 31) (14) The following two methods are characteristic of the conversion method represented by the above equations (5) to (14).

1. The physical general-purpose registers 0 to 7 and the physical floating-point registers are used in common for each window. These registers are global register
As er, data common to the operation loop using each window is held.

2. Regarding the physical floating point registers (FIG. 1), the logical floating point registers 28 to 31 of each window are the same physical floating point registers as the logical floating point registers 8 to 11 of the window whose window pointer is one larger. Point to.

Regarding the physical general-purpose register (FIG. 2), when the logical general-purpose register number is converted into the physical general-purpose register number, the logical general-purpose register 28 of each window is used.
The numbers 31 to indicate the same physical general registers as the logical general registers 8 to 11 of the window whose window pointer is larger by one. When the logical floating-point register number is converted to the physical general registers, The logical floating point register numbers 28 to 31 indicate the same physical general purpose registers as the logical floating point register numbers 8 to 11 of the window whose window pointer is larger by one.

These registers are over-lapp
It is used to transfer data between operation loops that use adjacent windows as the ing register.

The instruction mnemonics and functions of the new instruction are as follows:
As an example, it is determined as follows.

Here, the following extended floating-point register preload instruction, which is not described above, is newly provided as an instruction obtained by extending the function of the floating-point register preload instruction.

1. Current floating point window pointer change instruction (instruction mnemonic) CFRWPS GRm (Function) Sets the value of the general-purpose register m to the current floating point window pointer. 2. Current general-purpose window pointer change instruction (instruction mnemonic) CGRWPS GRm (Function) Sets the value of general-purpose register m to the current general-purpose window pointer.

3. Floating point register preload instruction (instruction mnemonic) FLDPRM a (GRm), FR
n (Function) 8-byte data is read from the main memory address represented by the value of the general-purpose register m and stored in the floating-point register n. At this time, logical floating-point register number-physical floating-point register number conversion is performed using (current floating-point window pointer + 1) as the current floating-point window pointer, and using the current general-purpose window pointer, logical general-purpose register number-physical general-purpose register Number conversion is performed.

Thereafter, the value of the general-purpose register m is added by a.
At this time, logical general-purpose register number-physical general-purpose register number conversion is performed using the current general-purpose window pointer.

4. Extended floating point register preload instruction (instruction mnemonic) FLDPRE a (GRm), FR
n (Function) 8-byte data is read from the main memory address represented by the value of the general-purpose register m and stored in the floating-point register n. At this time, logical floating-point register number-physical floating-point register number conversion is performed using (current floating-point window pointer + 2) as the current floating-point window pointer. Number conversion is performed.

Thereafter, the value of the general-purpose register m is added by a.
At this time, logical general-purpose register number-physical general-purpose register number conversion is performed using the current general-purpose window pointer.

5. Floating-point register post store instruction FSTPOM a (GRm), FRn (Function) Stores the value (8 bytes) of floating-point register n at the main memory address represented by the value of general-purpose register m. At this time, (current floating point window pointer-
Using 1) as the current floating-point window pointer, logical floating-point register number-physical floating-point register number conversion is performed, and logical general-purpose register number-physical general-purpose register number conversion is performed using the current general-purpose window pointer.

Thereafter, the value of the general-purpose register m is added by a.
At this time, logical general-purpose register number-physical general-purpose register number conversion is performed using the current general-purpose window pointer.

6. Floating-point register reload instruction (instruction mnemonic) FLDLI, FRn (Function) Reads 8 bytes of data from the main memory address represented by the value of general-purpose register n and stores it in floating-point register n. At this time, regarding the logical floating-point number n, the logical floating-point register number-physical floating-point register number conversion is performed using (current floating-point window pointer + 1) as the current floating-point window pointer.
With respect to the logical floating-point register number n, the logical floating-point register number-physical general-purpose register number conversion is performed using (current general-purpose window pointer + 1) as the current general-purpose window pointer.

7. General-purpose register reload instruction (instruction mnemonic) GLDLIM a (GRm), GR
n (Function) 8-byte data is read from the main memory address represented by the value of the general-purpose register m, and stored in the general-purpose register n. At this time, logical general-purpose register number-physical general-purpose register number conversion is performed using (current general-purpose window pointer + 2) as the current general-purpose window pointer for logical general-purpose register number n, and logical general-purpose register m is logically general-purpose using the current general-purpose window pointer. Register number-physical general-purpose register number conversion is performed.

Thereafter, the value of the general-purpose register m is added by a.
At this time, logical general-purpose register number-physical general-purpose register number conversion is performed using the current general-purpose register window pointer.

8. Floating-point register list store instruction (Instruction mnemonic) FSTLI FRn (Function) Stores the value (8 bytes) of floating-point register n in the main memory address represented by the value of general-purpose register n. At this time, with respect to the logical floating-point register number n, (current floating-point window pointer-1) is used as the current floating-point window pointer, logical floating-point register number-physical floating-point register number conversion is performed. With respect to n, the logical floating-point register number-physical general-purpose register number conversion is performed using (current general-purpose window pointer-1) as the current general-purpose window pointer.

In addition, a general floating-point instruction (ie,
In the instruction using the floating-point register except the above 3-8), the current floating-point window pointer is used to
Logical floating-point register number-physical floating-point register number conversion is performed. In general general-purpose instructions (that is, instructions using general-purpose registers and excluding the above 3-8), logical general-purpose register number-physical general-purpose register number conversion is performed using the current general-purpose window pointer.

Equation (1) of the source index type operation is
When the new function is used, a program as shown in Table 7 is obtained.

[0094]

[Table 7]

Here, it is assumed that prior to the execution of the program in Table 7, the vector L is stored in a continuous area starting from the main storage address ad1. That is, L
The main storage address of (1) is stored as ad1, and the main storage address of L (2) is stored as ad1 + 8. Similarly, it is assumed that the vector A is stored in a continuous area starting from the main storage address ad2. Also, the vector B
Is stored in a continuous area starting from the main storage address ad3. Ad1 for general register 1, ad2 for general register 2, N-3 for general register 4, 1 for general register 5, 0 for general register 6, 0 for current floating point window pointer, current general It is assumed that 0 is stored in the window pointer and 1 is stored in the current window pointer valid register. Here, as described above, the vector L is obtained by modifying the list vector Li as shown in Expression (4).

Here, Table 7 shows ADs not described above.
Since the D instruction and the SUB instruction are included, the functions of the two instructions will be described below.

ADD GRj, GRm (Function) The value of the general-purpose register j and the value of the general-purpose register m are added and stored in the general-purpose register j.

SUB GRj, GRm (Function) The value of general-purpose register m is subtracted from the value of general-purpose register j and stored in general-purpose register j.

Hereinafter, Table 7 will be described. No. In the GLDM instruction of No. 1, the logical general-purpose register number-physical general-purpose register number conversion is performed by the current general-purpose window pointer. > Is stored. N
o. In the FLDM instruction No. 2, the logical general-purpose register number-physical general-purpose register number conversion is performed by the current general-purpose window pointer, and the logical floating-point register number-physical floating-point register number conversion is performed by the current floating-point window pointer. 0, 20> at the address indicated by L (1), that is, B
(Li (1)) is a physical floating point register <0, 20>
Is stored in

No. In the ADD instruction of No. 3, the logical general-purpose register 6 is specified, and the register is the physical general-purpose register 6 according to the equation (10) (that is, Global).
register), the value of the physical general-purpose register 6 is set to 1. No. 4 sets the value of the physical general-purpose register 6 to the current floating-point window pointer by the CFRWPS instruction, that is, sets the value to 1. Similarly, No. 5 CGR
The value of the physical general-purpose register 6 is set to the current general-purpose window pointer by the WPS instruction, that is, the value is set to 1.

No. In the GLDM instruction No. 6, since the conversion of the logical general-purpose register number to the physical general-purpose register number is performed using the current general-purpose window pointer, L (2), ie, “B
(Li (2)) address ”is stored in the physical floating-point register <1, 20>. No. In the FLDM instruction No. 7, the conversion of the logical general-purpose register number to the physical general-purpose register number is performed by the current general-purpose window pointer, and the conversion of the logical floating-point register number to the physical floating-point register number is performed by the current floating-point window pointer. The main storage data of the address indicated by L (2) stored in <1,20>, that is, B (Li (2)) is stored in the physical floating point register <1,20>. No. 8
The value of the physical general-purpose register 6 is set to 2 by the ADD instruction. N
o. The value of the physical general-purpose register 6 is set to the current floating-point window pointer by the CFWWPS instruction of No. 9, that is, the value is set to 2. Similarly, No. The value of the physical general-purpose register 6 is set to the current general-purpose window pointer by the 10 CGRWPS instruction, that is, the value is set to 2.

No. In the GLDM instruction No. 11, since the logical general-purpose register number-physical general-purpose register number conversion is performed using the current general-purpose window pointer, L (3), ie, “B
(Li (3) address) is stored in the physical floating-point register <2, 20>.

No. The value of the physical general-purpose register 6 is set to 1 by the 12 SUB instructions. No. 13 physical general register 6 to the current floating-point window pointer with 13 CFRWPS instructions
Is set, that is, the value is set to 1. Similarly N
o. The value of the physical general-purpose register 6 is set to the current general-purpose window pointer by the 14 CGRWPS instructions, that is, the value is set to 1.

No. No. 15 from the GLDLIM instruction.
Up to 21 BCNT instructions constitute a loop and are executed N-3 times. Hereinafter, the value of the current floating-point window pointer in the loop is denoted by w, and the value of the current general-purpose window pointer is denoted by WG. Let us look at the loop executed at the i-th time (i starts from 2). Physical general register 1
As can be seen from the values of No. What is loaded into the physical general-purpose register <WG + 2, 20> by the 15 GLDLIM instructions is L (i + 2), that is, “the address of B (Li (i + 2))”. Physical general-purpose register <WG + 1, 20>
As can be seen from the values of No. It is B (Li (i + 1)) that is loaded into the physical floating point register <w + 1, 20> by the 16 FLDLI instructions. As can be seen from the value of general-purpose register 2, 17, the value of the physical floating-point register <w-1, 20> is A (i-
It is stored in the main storage location of 1). No. No. 18 ADD instruction, No. 18 19 CFWWPS instruction, No. 19 20 CGs
With the RWPS instruction, the current floating point window pointer w is +
In addition, the current general-purpose window pointer WG is incremented by one, and returns to the beginning of the loop.

That is, in one loop, if the value of the current floating-point window pointer in the loop is w and the value of the current general-purpose window pointer is WG, the physical value of the next loop is The address of the data B (Li (i + 2)) stored in the floating-point register <w + 2, 20>, that is, L (i + 2) is stored in the physical general-purpose register <WG + 2, 20>.
> In the previous loop, and the physical general-purpose register <WG +
1,20>, that is, L (i + 1), ie, “B (L
i (i + 1)) to B (Li (i + 1))
Is read, and the physical floating-point register <w + 1, 20
>. B (Li (i-1)) stored in the physical floating point register <w-1, 20> in the previous loop
Is stored in the main storage location of A (i-1).

No. after exiting the loop. No. 22 to No. 22.
The instruction of No. 28 is processing of an unprocessed element. 23
B (Li (N-2)) is converted to A (N-
No. 2) is stored in the main memory address. B (Li (N-1)) is converted to A (N-
No. 1) is stored in the main memory address. B (Li (N)) is stored in the main storage address of A (N) by the 28 FSTM instruction. As can be seen from the processing in the loop, No. 15, the logical general-purpose register 20 is designated by the GLDLIM instruction, and data is written into the general-purpose register. Logical general register 2 with 16 FLDLI instructions
The general-purpose register is read out by designating 0, but the physical general-purpose registers being accessed are <wG + 2, 20> and <
wG + 1,20>, which is different. No. 16 FLDs
The logical floating point register number 20 is designated by the LI instruction, and the data is written to the floating point register. 1
7 FSPOM instruction, logical floating point register number 2
Reading from the floating point register is performed by designating 0, but the physical floating point registers accessed are <w + 1, 20> and <w−1, 20>, which are different. Therefore, the phenomenon that the execution of the subsequent instruction is waited while waiting for data reading, which occurs in the program of Table 1, does not occur. In other words, the data reading is completed by the execution of the next loop. That is why the program runs at high speed. Also, the vector data specified in the program
There is only one logical floating-point register and one logical general-purpose register for storing data, and there is no need to use many floating-point registers and general-purpose registers as in the program of Table 4.

Here, the program of Table 7 has a process of updating the current floating-point window pointer and the current general-purpose window pointer which is not included in the program of Table 1, and thus has an overhead. For example, the program rule in Table 1
While the loop is composed of four instructions, the loop of the program in Table 7 is composed of seven instructions. However, the overhead of waiting for data reading in the program of Table 1 and waiting for the execution of the subsequent instruction is much larger. Also, the loop unrolling method as shown in the program of Table 4 cannot be realized if the registers that can be specified by the program are exhausted, so that there is overhead for updating the current floating-point window pointer and the current general-purpose window pointer. However, it is considered that the method of the present invention is superior. Next, when the above-mentioned new function is used for the expression (2) of the target index type operation, a program as shown in Table 8 is obtained.

[0108]

[Table 8]

Here, it is assumed that the vector L is stored in a continuous area starting from the main storage address ad1 prior to the execution of the program shown in Table 8. That is, L
The main storage address of (1) is stored as ad1, and the main storage address of L (2) is stored as ad1 + 8. Similarly, the vector B is stored in a continuous area starting from the main storage address ad2. It is assumed that the vector A is stored in a continuous area starting from the main storage address ad3. Ad1 for general register 1, ad2 for general register 2, N-3 for general register 4, 1 for general register 5, 0 for general register 6, 0 for current floating point window pointer, current general It is assumed that 0 is stored in the window pointer and 1 is stored in the current window pointer valid register. Here, as described above, the vector L is obtained by modifying the list vector Li as shown in Expression (4).

Hereinafter, Table 8 will be described. No. In the GLDM instruction of No. 1, since the conversion of the logical general-purpose register number to the physical general-purpose register number is performed by the current general-purpose window pointer, L (1), that is, the “address of A (Li (1))” is set to the physical general-purpose register <0, 20. > Is stored. N
o. In the FLDM instruction No. 2, B (1) is stored in the physical floating-point register <0, 20> because the logical floating-point register number-physical floating-point register number conversion is performed by the current floating-point window pointer.

No. 3, the value of the physical general-purpose register 6 is set to 1 (the general-purpose register 6 is
Since the register is a register, the logical general-purpose register number-physical general-purpose register number is not converted.) No. 4 CFRW
The value of the physical general-purpose register 6 is set to the current floating-point window pointer by the PS instruction, and the value is set to 1. Similarly N
o. The value of the physical general-purpose register 6 is set to the current general-purpose window pointer by the CGRWPS instruction of No. 5, and the value is set to 1.

No. In the GLDM instruction No. 6, since the conversion of the logical general-purpose register number to the physical general-purpose register number is performed using the current general-purpose window pointer, L (2), ie, “A
(Li (2) address) is a physical general-purpose register <1,
20>. No. In the FLDM instruction No. 7, B (2) is stored in the physical floating-point register <1, 20> because the logical floating-point register number-physical floating-point register number conversion is performed by the current floating-point window pointer.

No. 8, the value of the physical general-purpose register 6 is set to 2 (the general-purpose register 6 is
Since the register is a register, the logical general-purpose register number-physical general-purpose register number is not converted.) No. 9 CFRW
The value of the physical general-purpose register 6 is set to the current floating-point window pointer by the PS instruction, and the value is set to 2. Similarly N
o. The value of the physical general-purpose register 6 is set to the current general-purpose window pointer by the 10 CGRWPS instruction, and the value is set to 2.

No. In the GLDM instruction of No. 11, since the conversion of the logical general-purpose register number to the physical general-purpose register number is performed using the current general-purpose window pointer, L (3), that is, “A
(Li (3)) address is a physical general-purpose register <2,
20>.

No. The value of the physical general-purpose register 6 is set to 1 by the 12 SUB instructions. No. 13 physical general register 6 to the current floating-point window pointer with 13 CFRWPS instructions
Is set, and the value is set to 1. Similarly, No. 14 C
The value of the physical general-purpose register 6 is set to the current general-purpose window pointer by the GRWPS instruction, and the value is set to 1.

No. No. 15 from the GLDLIM instruction.
Up to 21 BCNT instructions constitute a loop and are executed N-3 times. Hereinafter, the value of the current floating-point window pointer in the loop is denoted by w, and the value of the current general-purpose window pointer is denoted by WG. Let us look at the loop executed at the i-th time (i starts from 2). As can be seen from the value of general-purpose register 1, No. The 15 GLDLIM instructions loaded into the physical general-purpose register <WG + 2, 20>
L (i + 2), that is, “address of A (Li (i + 2))”. As can be seen from the value of general register 2, N
o. It is B (i + 1) that is loaded into the physical floating point register <w + 1, 20> by the 16 FLDPRM instructions. No. In 17 FSTLI instructions, the value of the physical floating-point register <w + 1, 20>, that is, B (i−1)
Is stored in the main storage location of A (Li (i-1)). N
o. No. 18 ADD instruction, No. 18 19 CFWWPS instruction, No. 19 The current floating-point window pointer w is incremented by 1 with the 20 CGRWPS instructions, and the current general-purpose window pointer WG is incremented by 1 to return to the beginning of the loop.

That is, in one loop, assuming that the value of the current floating-point window pointer in the loop is w and the value of the current general-purpose window pointer is WG, B in the next three loops Address L (i + 2) for storing (i + 2)
That is, the “address of A (Li (i + 2))” is stored in the physical general-purpose register <WG + 2, 20>, and the next two
B (i + 1) stored in the main memory by the loop is stored in the physical floating-point register <w + 1,20>, and the L (L + 1) stored in the physical general-purpose register <WG-1,20> by the loop three before is stored.
(I-1), ie, "address of A (Li (i-1))", the physical loop register <w
-1, 20> is stored.

No. after exiting the loop. No. 22 to No. 22.
The instruction of No. 28 is processing of an unprocessed element. 23
B (N-2) with A (Li (N-
2)) is stored in the main memory address, and 27
B (N-1) with A (Li (N-
1)) is stored in the main storage address, and No. 1 is stored. 28
B (N) is stored in the main storage address of A (Li (N)) by the FSTM instruction.

As can be seen from the processing in the loop, N
o. Logical general register number 2 with 15 GLDLIM instructions
0 is designated, and writing is performed to the general-purpose register.
The FSTLI instruction of No. 17 specifies the logical floating-point register number 20 to read the general-purpose register, but the physical general-purpose register being accessed is <WG + 2, 20>
And <WG-1, 20>, which are different. No. 16 F
The data is written to the floating-point register by designating the logical floating-point register number 20 by the LDPRM instruction. The FSTLI instruction of No. 17 specifies the logical floating-point register number 20 to read the floating-point register, but the physical floating-point register being accessed is <w
+1 and 20> and <w−1, 20>, which are different from each other. Therefore, the phenomenon that the execution of the subsequent instruction is waited while waiting for data reading, which occurs in the program of Table 2, does not occur. In other words, the data reading is completed by the execution of the next loop. That is why the program runs at high speed. Further, there is only one logical floating point register and one logical general purpose register for storing the vector data specified by the program, and there is no need to use many floating point registers and general purpose registers as in the program of Table 5.

Here, the program in Table 8 has a process of updating the current floating-point window pointer and the current general-purpose window pointer which is not included in the program in Table 2, and thus has an overhead. For example, the program rule in Table 2
While the loop is composed of four instructions, the loop of the program in Table 8 is composed of seven instructions. However, the overhead of waiting for data reading in the program of Table 2 and waiting for execution of the subsequent instruction is much larger. Also, the loop unrolling method as in the program of Table 5 cannot be realized if the registers that can be specified by the program are exhausted, so that the overhead of updating the current floating-point window pointer and the current general-purpose window pointer is required. However, it is considered that the method of the present invention is superior.

Next, when the equation (3) of the particle propulsion type calculation is used with the above-described new function, a program as shown in Table 9 is obtained.

[0122]

[Table 9]

Here, it is assumed that the vector L is stored in a continuous area starting from the main storage address ad1 prior to the execution of the program shown in Table 9. That is, L
The main storage address of (1) is stored as ad1, and the main storage address of L (2) is stored as ad1 + 8. Similarly, it is assumed that the vector A is stored in a continuous area starting from the main storage address ad3. Also, the vector B
Is stored in a continuous area starting from the main storage address ad2. Ad1 for general register 1, ad2 for general register 2, N-3 for general register 4, 1 for general register 5, 0 for general register 6, 0 for current floating point window pointer, current general It is assumed that 0 is stored in the window pointer and 1 is stored in the current window pointer valid register. Here, as described above, the vector L is obtained by modifying the list vector Li as shown in Expression (4).

Hereinafter, Table 9 will be described. No. In the GLDM instruction of No. 1, since the conversion of the logical general-purpose register number to the physical general-purpose register number is performed by the current general-purpose window pointer, L (1) is stored in the physical general-purpose register <0, 20>. No. In the FLDM instruction No. 2, since the conversion of the logical floating-point register number to the physical floating-point register number is performed by the current floating-point window pointer and the conversion of the logical general-purpose register number to the physical general-purpose register number is performed by the current general-purpose window pointer, L (1) Is stored in the physical floating point register <0, 20>. No. In the FLDM instruction 3, the logical floating point register number-physical floating point register number conversion is performed using the current floating point window pointer.
21>. No. In the FADD instruction No. 4, since the logical floating-point register number-physical floating-point register number conversion is performed by the current floating-point window pointer, the value of the physical floating-point register <0, 20> and the physical floating-point register <0, 21> , And the result, that is, “A (Li (1)) + B (1)” is stored in the physical floating-point register <0, 20>.

No. With the ADD instruction of 5, the value of the physical general-purpose register 6 is set to 1 (the general-purpose register 6 is a global register according to the equation (10)). No. 6 CF
The value of the physical general-purpose register 6 is set to the current floating-point window pointer by the RWPS instruction, that is, the value is set to 1. Similarly, No. 7, the value of the physical general-purpose register 6 is set in the current general-purpose window pointer by the CGRWPS instruction 7, that is, the value is set to 1. No. In the GLDM instruction of No. 8, since the conversion of the logical general-purpose register number to the physical general-purpose register number is performed using the current general-purpose window pointer, L (2)
That is, the “address of A (Li (2))” is stored in the physical general-purpose register <1, 20>. No. 9 FLDM
In the instruction, logical floating-point register number-physical floating-point register number conversion is performed by the current floating-point window pointer, and logical general-purpose register number-physical general-purpose register number conversion is performed by the current general-purpose window pointer.
The main memory data of the address indicated by (2), that is, A (Li
(2)) is stored in the physical floating-point register <1, 20>. No. In the FLDM instruction No. 10, since the logical floating point register number-physical floating point register number conversion is performed by the current floating point window pointer, B
(2) is stored in the physical floating-point register <1, 21>.

No. The value of the physical general-purpose register 6 is set to 2 by the 11 ADD instruction. No. The value of the physical general-purpose register 6 is set to the current floating-point window pointer by the 12 CFRWPS instructions, that is, the value is set to 2. Similarly N
o. The value of the physical general-purpose register 6 is set to the current general-purpose window pointer by the 13 CGRWPS instruction, that is, the value is set to 2.

No. In the GLDM instruction of No. 14, since the logical general-purpose register number-physical general-purpose register number conversion is performed by the current general-purpose window pointer, L (3), that is, "A
(Li (3)) address is a physical general-purpose register <2,
20>. No. The value of the physical general-purpose register 6 is set to 1 by the 15 SUB instructions. No. 16 CFRW
The value of the physical general register 6 is set to the current floating point window pointer by the PS instruction, that is, the value is set to 1.
Similarly, No. The value of the physical general-purpose register 6 is set to the current general-purpose window pointer by the 17 CGRWPS instruction, that is, the value is set to 1.

No. No. 18 from the GLDLIM instruction.
Up to 26 BCNT instructions constitute a loop and are repeatedly executed N-3 times. Hereinafter, the value of the current floating-point window pointer in the loop is denoted by w, and the value of the current general-purpose window pointer is denoted by WG. Let us look at the loop executed at the i-th time (i starts from 2). As can be seen from the value of general-purpose register 1, No. What is loaded to the physical general-purpose register <WG + 2, 20> by the 18 GLDLIM instruction is
L (i + 2), that is, “address of A (Li (i + 2))”. As can be seen from the physical general-purpose register <WG + 1, 20>, What is loaded into the physical floating-point register <w + 1, 20> by the 19 FLDLI instructions is A
(Li (i + 1)), and as can be seen from the value of the general-purpose register 2, No. What is loaded into the physical floating point register <w + 1, 21> by the 20 FLDPRM instructions is B
(I + 1). No. 21, the value of the physical floating point register <w, 20>, that is, A (Li
(I)) and the value of the physical floating-point register <w, 21>, that is, B (i), are added, and the physical floating-point register <
w, 20>. No. In the FSTLI instruction No. 21, the value of the physical floating-point register <w-1, 20>, that is, "A (Li (i-1)) + B (i-1)" is indicated by the general-purpose register <WG-1, 20>. Main memory address, i.e., L (i-1) (i.e., "A (Li (i-
1)) address)). No. 23 AD
D instruction, No. 24 CFRWPS instruction, No. 24 25 CGRWPS instructions, the current floating point window pointer w
Is incremented by 1, and the current general-purpose window pointer WG is incremented by +
1 is returned to the beginning of the loop.

That is, in one loop, if the value of the current floating-point window pointer in the loop is w and the value of the current general-purpose window pointer is WG, no. 18
GLDLIM instruction, the data A (L) stored in the physical floating-point register <w + 2, 20> in the next loop
i (i + 2)) at address L (i + 2), ie, “A
(Li (i + 2) address) is read from the main memory and stored in the physical general-purpose register <WG + 2, 20>.
o. With the FLDLI instruction of No. 19, L (i +) stored in the physical general-purpose register <WG + 1, 20> in the immediately preceding loop
1), that is, A (Li (i + 1)) is read from “address of A (Li (i + 1))” and stored in the physical floating-point register <w + 1, 20>. 20 FLDs
In the PRM instruction, the data used for addition in the next loop
Data B (i + 1) is stored in the physical floating-point register <w + 1,2
1>. With the 21 FADD instruction, the previous loop
Loaded into the physical floating-point register <w, 20> and the physical floating-point register <w, 21>, respectively.
(Li (i)) and B (i) are added and stored in the physical floating-point register <w, 20>. 22 FS
In the TLI instruction, A (Li (i−i) stored in the physical floating-point register <w−1, 20> in the previous loop.
1)) + B (i-1) is the main memory address loaded into the physical general-purpose register <WG-1, 20>, ie, L (i-1) (that is, "A ( Li (i-
1)))).

No. after exiting the loop. 28 to No. 28
The instruction No. 36 is processing of an unprocessed element. 30
A (Li (N-2)) + B (N-
2) is stored in the main storage address of A (Li (N−2)), and No. 2 is stored. A (Li (N
-1)) + B (N-1) is stored in the main memory address of A (Li (N-1)). 36 FSTM
A (Li (N)) + B (N) is converted to A (Li (N))
Is stored in the main storage address.

As can be seen from the processing in the loop, N
o. Logical general register number 2 by 18 GLDLIM instructions
0 is designated, and writing is performed to the general-purpose register.
Logical floating point register number 2 with 19 FLDLI instructions
The general-purpose register is read by designating 0, but the physical general-purpose register being accessed is <WG + 2, 20>
And <WG + 1,20>, which are different. In addition, No. 1
Floating point register number 20 by FLDLI instruction 9
And write data to the floating-point register.
o. Reading from the floating-point register by designating the logical floating-point register number 20 with the 21 FADD instruction, the physical floating-point registers being accessed are <w + 1, 20> and <w, 20>. different. In addition, No. 20, the data is written to the floating-point register by designating the logical floating-point register number 21 with the FLDPRM instruction of No. 20; Reading is performed from the floating-point register by designating the logical floating-point register number 21 with the 20 FADD instructions, but the physical floating-point registers accessed are <w + 1, 21> and <w, 21>. different. In addition, No. The logical floating-point register number 20 is designated by the FADD instruction of No. 21 and the floating-point register is written. The FSTLI instruction No. 22 specifies the logical floating-point register number 20 to read from the floating-point register, but the physical floating-point registers being accessed are <w, 20> and <w-1,
0>, which is different. Therefore, the phenomenon that the execution of the subsequent instruction is waited while waiting for data reading, which occurs in the program of Table 3, does not occur. In other words, the data reading is completed by the execution of the next loop. All you have to do is
The program runs fast. Also, there are two logical floating-point registers and only one logical general-purpose register for storing vector data specified by the program.
It is not necessary to use many floating-point registers and general-purpose registers as in the program of Table 6.

Here, the program in Table 9 has a process of updating the current floating-point window pointer and the current general-purpose window pointer which is not included in the program in Table 3, and thus has an overhead. For example, the program rule in Table 3
While the loop is composed of six instructions, the loop of the program in Table 9 is composed of nine instructions. However, the overhead of waiting for data reading in the program of Table 3 and waiting for the execution of a subsequent instruction is much larger. Also, the loop unrolling method as shown in the program of Table 6 cannot be realized if the registers that can be specified by the program are exhausted, so that there is overhead for updating the current floating point window pointer and the current general-purpose window pointer. However, it is considered that the method of the present invention is superior.

As described above, according to the method of the present invention, in the list vector operation in the vector calculation of the scientific and technical calculation in which the loop of the instruction sequence is mainly performed, the current floating point window pointer is provided for each loop. And the current general-purpose window pointer is changed, that is, the window to be used is changed. In the source index type operation, the processing of the i-th element is performed by the general register list load instruction by the general-purpose register list load instruction in the (i-2) -th loop. Load the i-th element to the general-purpose register.
A list of source vectors (vectors to be read) by a floating-point register list load instruction in the (i-1) -th loop using data in the general-purpose register as a main memory address. Loading the element indicated by the ith element of the vector into the floating-point register, and floating the target vector (the vector to be written) to the ith element by the floating-point register post-store instruction in the (i + 1) -th loop. By storing the data in the decimal point register, the load of the list vector for one element number, the load of the source vector, and the processing of the store to the target vector are performed on the instruction sequence. The distance increases,
The performance can be prevented from being degraded due to the influence of the data reading time, and the speed can be increased. In the target index type operation, the processing of the i-th element is performed by the general register list in the (i-2) -th loop. Load the ith element of the list vector to the general-purpose register by the load instruction, and the ith element of the source vector (vector to be read) by the floating point register preload instruction in the (i-1) -th loop And loading data in the floating-point register using the data in the general-purpose register as a main memory address by the floating-point register list store instruction in the (i + 1) -th loop. By storing the target vector in the “element indicated by the i-th element of the list vector”, the load and source of the list vector for one element number are performed. The load on the instruction and the distance in the instruction sequence for the processing of the store to the target vector are increased, the performance can be prevented from deteriorating due to the influence of the data read time, and the speed can be increased. In the propulsion type operation, the processing of the i-th element is performed by loading the list vector into the general-purpose register of the i-th element by the general-purpose register list load instruction in the (i-2) -th loop. Of the first vector (i.e., vector A in equation (3)) by the floating point register reload instruction in the
Loads the element pointed to by the first floating-point register.
Loading the i-th element of the second vector (i.e., the vector B in equation (3)) into the second floating-point register by the floating-point register preload instruction, and adding the floating-point at the i-th loop. Instructions, the addition of the two floating point registers (i.e., the addition of the element indicated by the ith element of the list vector of the first vector and the ith element of the second vector), and the floating point register at the (i + 1) -th loop By performing a list store instruction to store the addition result in the “element indicated by the i-th element of the list vector of the first vector” using the value of the general-purpose register as a main storage address, one element number is obtained. , The first vector load, the second vector load (the first vector load and the second vector load have no correlation). In Ino, same Le - performed in-flop),
The distance between the addition of the elements of the first vector and the elements of the second vector and the processing of storing the addition result in the first vector on the instruction sequence becomes large, and the influence of the data reading time and the operation execution time is increased. The performance can be prevented from lowering, and the speed can be increased.

[0134]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a data processing apparatus according to the present embodiment. The data processing device includes an instruction processing unit 10 for issuing and executing instructions, a main memory 30 for storing instructions and data to be executed by the instruction processing unit, and data between the instruction processing unit and the main memory. And a storage control unit 20 for controlling the exchange of data.

The instruction processing unit 10 has an instruction register 101 for holding an instruction to be executed, an instruction control unit 10 for decoding the contents of the instruction register 101 and controlling the instruction execution.
2. Physical general-purpose register group 103 for holding data required for general-purpose operation and address calculation, general-purpose arithmetic unit 104 for executing general-purpose operation specified by an instruction, and physical for holding data required for floating-point operation Floating point register group 10
5. Floating point arithmetic unit 106 for executing a floating point operation specified by the instruction, address adder 107 for calculating a main storage address for accessing main storage data, and a main read from storage control unit 20 A cache 108 for holding storage data, a main storage access control unit 109 for controlling reading of main storage data from the storage control unit 20 in accordance with a search result of the cache 108, and a current storage for a current floating point window pointer. Floating point window pointer register 110, current general-purpose window pointer register 1 for storing the current general-purpose window pointer
13, a current window pointer valid register 111 indicating that the current floating-point window pointer and the current general-purpose window pointer are valid, a signal 115 indicating a logical floating-point register number specified by an instruction, and a signal 115 as a physical floating-point register number. The first conversion circuit 112 for converting according to the equations (5)-(9), the signal 116 indicating the logical general-purpose register number specified by the instruction, the signal 115 or the signal 116 is converted into the physical general-purpose register number by the equation (10)-
It comprises a second conversion circuit 114 for converting according to (14). Note that the signal 115 and the signal 116 can transfer a plurality of register numbers for an instruction that specifies a plurality of general-purpose register numbers or a plurality of floating-point register numbers in the instruction.

Here, eight instructions are newly added to this data processing device, and FIG. 4 shows the instruction format. The additional instructions include (a) a current floating-point window pointer change instruction, (b) a current general-purpose window pointer change instruction,
(C) floating-point register preload instruction, (d) extended floating-point register preload instruction, (e) floating-point register post-store instruction, (f) floating-point register reload instruction, (g) general-purpose register reload instruction (H) floating point register list store instruction. The instruction mnemonics and functions of the instructions have been described in the section "Action".

The current floating point window pointer change instruction is an instruction for designating the current floating point window pointer. In FIG. 4A, the instruction code indicates that the instruction is a current floating-point window pointer change instruction. The general-purpose register number designates a general-purpose register in which the value of the current floating-point window pointer to be set is stored.

The current general-purpose window pointer change instruction is an instruction for designating the current general-purpose window pointer. FIG.
In (b), the instruction code indicates that the instruction is a current general-purpose window pointer change instruction. The general-purpose register number designates a general-purpose register in which the value of the current general-purpose window pointer to be set is stored.

The floating-point register preload instruction reads data from the main memory address indicated by the general-purpose register belonging to the current window, and stores the data in the floating-point register belonging to the (current floating-point window pointer + 1) window. It is. In FIG. 4C, the instruction code is:
This indicates that the instruction is a floating point register preload instruction. The floating-point register number is a logical floating-point register number (r), and the physical floating-point register number in which data is stored is <w + 1, r>, where w is the current floating-point window pointer. The general-purpose register number is a logical general-purpose register number (rG),
Assuming that the current general-purpose window pointer is wG, the value of the physical general-purpose register <wG, rG> is the main memory address from which data is read. After the reading, the value added to the physical general-purpose register <wG, rG> is an increment value.

The extended floating-point register preload instruction reads data from the main memory address indicated by the general-purpose register belonging to the current window and stores the data in the floating-point register belonging to the (current floating-point window pointer + 2) window. Instruction. In FIG. 4D, the instruction code
The command indicates that the instruction is an extended floating-point register preload instruction. The floating point register number is a logical floating point register number (r), and the physical floating point register number in which data is stored is <w + 2, r>, where w is the current floating point window pointer.
The general-purpose register number is a logical general-purpose register number (rG), and the current general-purpose window pointer is wG,
The value of the physical general-purpose register <wG, rG> is a main memory address from which data is read. After the reading, the value added to the physical general-purpose register <wG, rG> is an increment value.

The floating-point register post-store instruction is
This instruction reads data from the floating-point register belonging to the window of (current floating-point window pointer-1) and stores the data in the main memory address indicated by the general-purpose register belonging to the current window. The instruction code in FIG.
Indicates that the instruction is a floating-point register post-store instruction. The floating-point register number is a logical floating-point register number (r), and the physical floating-point register number from which data is read is <w-1, r>, where w is the current floating-point window pointer. . The general-purpose register number is a logical general-purpose register number (rG), and the value of the physical general-purpose register <wG, rG> is a main storage address where data is stored, with the current general-purpose window pointer being wG. After the reading, the value added to the physical general-purpose register <wG, rG> is an increment value.

The floating-point restore load instruction reads data from the main memory address indicated by the general-purpose register belonging to the window of (current general-purpose window pointer + 1), and reads the data of floating-point number belonging to the window of (current floating-point window pointer + 1). This is an instruction to be stored in a register. FIG.
In (f), the instruction code indicates that the instruction is a floating-point register reload instruction. The floating-point register number is a logical floating-point register number (r), and the current floating-point window pointer is w, and the physical floating-point register number in which data is stored is <w +
1, r>. The general-purpose register number is a logical general-purpose register number (rG), and the value of the physical general-purpose register <wG + 1, rG> is a main storage address from which data is read, with the current general-purpose window pointer being wG.

The general-purpose register list load instruction is an instruction for storing data in the general-purpose register belonging to the window of (current general-purpose window pointer + 2) from the main memory address indicated by the general-purpose register belonging to the current window.
In FIG. 4 (g), the instruction code is a general-purpose register reload.
This indicates that the instruction is a command. The general-purpose register number 1 is a logical general-purpose register number (rG1). The value of the physical general-purpose register <wG, rG1> is a main storage address from which data is read, with the current general-purpose window pointer being wG. The general-purpose register number 2 is a logical general-purpose register number (rG2), and the number of a physical general-purpose register in which data is stored is <wG + 2, rG2>.
After the execution of the reading, the value added to the physical general-purpose register <wG, rG1> is the increment value.

The store floating point register list instruction is
Data is read from the floating point register belonging to the window of (current floating point window pointer -1),
This is an instruction to be stored in the main memory address indicated by the general-purpose register belonging to the window of (current general-purpose window pointer-1). In FIG. 4H, the instruction code indicates a floating-point register list store instruction. The floating-point register number is a logical floating-point register number (r), and the physical floating-point register number from which data is read is <w-1, r>, where w is the current floating-point window pointer. . Assuming that the current general-purpose window pointer is wG, the physical general-purpose register <wG-1, r
The value of> is the main memory address where the data is stored.

The operation of these instructions will be described with reference to FIG. First, the current floating point window pointer change instruction will be described. When the instruction is loaded into the instruction register 101, the instruction is decoded by the instruction control unit 102. When the instruction is identified as the current floating-point window pointer change instruction, the general-purpose register specified in the instruction is read. , The value stored in the register is set in the current floating point window pointer register 110.

Next, the current general-purpose window pointer change instruction will be described. When the instruction is loaded into the instruction register 101, the instruction is decoded by the instruction control unit 102. When the instruction is identified as the current general-purpose window pointer change instruction, the general-purpose register specified in the instruction is read out.
The value stored in the register is set in the current general-purpose window pointer register 113. Next, the floating-point register preload instruction will be described. When an instruction is taken into the instruction register 101,
The instruction is decoded by the instruction control unit 102. When the instruction is identified as a floating-point register preload instruction, a logical general register number (rG), which is a general register number specified in the instruction, is transmitted via a signal 116. Second conversion circuit 11
4 and the current general-purpose window pointer register 11
Assuming that the value of 3 is wG, the second conversion circuit 114 converts the value into a physical general-purpose register <wG, rG>, and the address adder 1
Reference numeral 07 denotes the content of the physical general-purpose register as a main storage address for reading data from the main storage. The main memory access control unit 109 searches the cache 108 based on the main memory address. If desired data is found in the cache, the data is transferred from the cache. The data is transferred from the main memory 30. The transfer data is stored in the floating point register 105. The physical floating point register number of the stored floating point register is obtained by the first conversion circuit 112 as follows. The floating point register number specified in the instruction is a logical floating point register number (r), which is transferred to the first conversion circuit 112 via a signal 115, and the value of the current floating point window pointer register 110 is w. <W + 1, r> is the physical floating-point register number. After the data transfer operation starts, the general-purpose arithmetic unit 1
At step 04, an increment value is added to the value of the physical general-purpose register <wG, rG>.

Next, the extended floating-point register preload instruction will be described. When the instruction is taken into the instruction register 101, the instruction is decoded by the instruction control unit 102,
If it is determined that the instruction is an extended floating-point register preload instruction, a logical general register number (rG), which is a general register number specified in the instruction, is transferred to the second conversion circuit 114 via a signal 116, and Assuming that the value of the current general-purpose window pointer register 113 is wG, it is converted into a physical general-purpose register <wG, rG> by the second conversion circuit 114, and the address adder 107 mainly stores the data of the physical general-purpose register as data. It is a main storage address for reading from storage. The main memory access control unit 109 searches the cache 108 based on the main memory address. If desired data is found in the cache, the data is transferred from the cache. , Main memory 3
Data is transferred from 0. The transfer data is stored in the floating point register 105. The physical floating point register number of the stored register is obtained by the conversion circuit 112 as follows. The floating-point register number specified in the instruction is a logical floating-point register number (referred to as r), which is transferred to the first conversion circuit 112 via the signal 115, and the current floating-point window pointer register 11
Assuming that the value of 0 is w, <w + 2, r> is the physical floating-point register number. After the start of the data transfer operation, the general-purpose arithmetic unit 104 adds an increment value to the value of the physical general-purpose register <wG, rG>.

Next, the floating-point register post-store instruction will be described. When the instruction is loaded into the instruction register 101, the instruction is decoded by the instruction control unit 102. When the instruction is identified as a floating-point register post-store instruction, a logical general-purpose register number designated in the instruction is used. When the register number (rG) is transferred to the second conversion circuit 114 via the signal 116 and the value of the current general-purpose window pointer register 113 is wG, it is converted by the second conversion circuit 114 into the physical general-purpose register <wG, rG>. And
The address adder 107 uses the contents of the physical general-purpose register as a main memory address for storing data in the main memory. Data is read from the floating point register 105. The physical floating point register number of the register to be read is obtained by the conversion circuit 112 as follows. The floating-point register number specified in the instruction is a logical floating-point register number (referred to as r).
5 and is transferred to the first conversion circuit 112, and the value of the current floating-point window pointer
w-1, r> is the physical floating-point register number. The main memory access control unit 109 searches the cache 108 based on the main memory address, and if there is a copy of the data stored in the main memory address of the main memory 30 in the cache, the data is retrieved. Replace the data with the read data,
If not, the cache is not operated. Further, the main memory access control unit 109 stores the read data at the main memory address of the main memory 30 via the storage control unit 20. After the start of the data transfer operation, the general-purpose computing unit 104
Adds an increment value to the value of the physical general-purpose register <wG, rG>.

Next, the floating point register reload instruction will be described. When an instruction is loaded into the instruction register 101, the instruction is decoded by the instruction control unit 102, and when it is identified that the instruction is a floating point register reload instruction, the instruction is executed with the floating point register number specified in the instruction. A certain logical floating-point register number (r) is a signal 1
15, the value of the current general-purpose window pointer register 113 is defined as wG, and the second general-purpose conversion circuit 114 transfers the physical general-purpose register <wG + 1, r>
The address adder 107 uses the contents of the physical general-purpose register as a main memory address for reading data from the main memory. The main memory access control unit 109 searches the cache 108 based on the main memory address, and if desired data exists in the cache, the data is read from the cache.
If not, via the storage control unit 20,
The data is transferred from the main memory 30. The transfer data is stored in the floating point register 105. The physical floating point register number of the stored floating point register is obtained by the first conversion circuit 112 as follows. The floating-point register number specified in the instruction is the logical floating-point register number r, which is transferred to the first conversion circuit 112 via the signal 115, and the value of the current floating-point window pointer register 110 is w, where <w + 1, r > Is the physical floating point register number.

Next, a general-purpose register reload instruction will be described. When the instruction is loaded into the instruction register 101, the instruction is decoded by the instruction control unit 102, and when the instruction is identified as a general register reload instruction, the first general register number designated in the instruction is read. Is transferred to the second conversion circuit 114 via the signal 116, and if the value of the current general-purpose window pointer register 113 is wG, the second conversion circuit 1
At 14, it is converted into a physical general-purpose register <wG, rG1>
The address adder 107 sets the contents of the physical general-purpose register as a main storage address for reading data from the main storage. The main memory access control unit 109 searches the cache 108 based on the main memory address. If desired data is found in the cache, the data is transferred from the cache. The data is transferred from the main memory 30. The transfer data is stored in the general-purpose register 10.
The physical conversion register number of the stored general-purpose register is obtained by the second conversion circuit 114 as follows. The logical general-purpose register number 2 (rG2), which is the second general-purpose register number specified in the instruction, is transferred to the second conversion circuit 114 via the signal 116, and
In the conversion circuit 114, the physical general-purpose register <wG + 2, rG2
>.

After the start of the data transfer operation, the general-purpose arithmetic unit 10
In step 4, an increment value is added to the value of the physical general-purpose register <wG, rG1>.

Next, the floating point register list store instruction will be described. If the instruction is loaded into the instruction register 101, the instruction is decoded by the instruction control unit 102. If it is determined that the instruction is a floating-point register list store instruction, data is read from the floating-point register 105. However, the physical floating-point register number of the register to be read out is obtained by the first conversion circuit 112 as follows. The floating point register number specified in the instruction is a logical floating point register number (r), which is transferred to the first conversion circuit 112 via a signal 115, and the value of the current floating point window pointer register 110 is w. <W-1, r> is the physical floating-point register number. The logical floating point register number r is the signal 115
When the value of the current general-purpose window pointer register 113 is set to wG, the value is converted to a physical general-purpose register number <wG-1, r>, and the address adder 107 stores the value of the physical general-purpose register. The content is a main storage address for storing data from the physical floating point register. The main memory access control unit 109 searches the cache 108 based on the main memory address, and if there is a copy of the data stored in the main memory address of the main memory 30 in the cache, the data is retrieved. Read the data
If it is not replaced, the cache is not operated. Further, the main memory access control unit 109 stores the read data at the main memory address of the main memory 30 via the storage control unit 20.

In addition, a general floating-point instruction (ie,
Instructions using floating-point registers, such as the floating-point register preload instruction, extended floating-point register preload instruction, floating-point register post-store instruction, floating-point register list load instruction, general-purpose register list load instruction, and floating-point register In instructions except for the decimal point register list store instruction), the current window pointer valid register 1
If 11 is “1”, the logical floating-point register number r indicated in the instruction is the physical floating-point register number indicated by <w, r>, where w is the value of the current floating-point window pointer register 110. Are converted by the first conversion logic 112, and the physical floating-point register indicated by the physical floating-point register number is referred to. If the current window pointer valid register 111 is “0”, the logical floating-point register number r indicated in the instruction becomes the first conversion logic 11
2, no conversion is performed, and the physical floating-point register indicated by the physical floating-point register number r is referred to.

A general-purpose instruction (ie, an instruction using a general-purpose register, such as the floating-point register preload instruction, the extended floating-point register preload instruction,
Instructions except floating-point register post store instruction, floating-point register list load instruction, general-purpose register list load instruction, and floating-point register list store instruction)
When the current window pointer valid register 111 is “1”, the logical general-purpose register number rG indicated in the instruction is the physical general number indicated by <wG, rG> where the value of the current general-purpose window pointer register 113 is wG. The data is converted into the general-purpose register number by the second conversion logic 114, and the physical general-purpose register indicated by the physical general-purpose register number is referred to. Current window pointer valid register 111 is "0"
Is the logical general register number rG indicated in the instruction.
Is not converted by the second conversion logic 114, and the physical general-purpose register indicated by the physical general-purpose register number rG is referred to.

The above floating point register preload instruction, extended floating point register preload instruction, floating point register post store instruction, floating point register list load instruction, general purpose register list load instruction, floating point register list store instruction If the current window pointer valid register 111 is “1”, the logical floating-point register number-physical floating-point register number conversion, logical floating-point register number-physical general-purpose register number conversion, logical general-purpose register Number-physical general-purpose register number conversion is performed, and the physical floating-point register or physical general-purpose register indicated by the converted number is referred to. When the current window pointer valid register 111 is “0”, the logical floating-point register number is equal to the physical floating-point register number and the logical floating-point register number is equal to the logical floating-point register number. Regarding the physical general register number conversion, the logical floating point register number is equal to the physical general register number, and the logical general register number−
Regarding the physical general register number conversion, the logical general register number is equal to the physical general register number.

Here, an empty bit of an existing register for storing control information of the data processing system may be assigned to the current window pointer valid register 111. An existing instruction for storing a value in the register is used. Value is set.

As described above, the current floating-point window pointer change instruction, current general-purpose window pointer change instruction, floating-point register preload instruction, extended floating-point register preload instruction, floating-point register poststore instruction, and floating-point register reload instruction Instruction, general register list load instruction, floating point register list store instruction, general floating point instruction under the control of the current floating point window pointer and the current general purpose window pointer, and general general instructions operate.

The fact that the above-described embodiments can realize the programs shown in Tables 7, 8, and 9 and that the list vector calculation is speeded up has been described in the column of "Action".

Therefore, according to the method of the present invention, by changing the current floating point window pointer, a certain floating point register number in the instruction is converted to a different physical floating point register number, and by changing the current general purpose window pointer, Since the number of a floating-point register or a general-purpose register in an instruction is converted into a different physical general-purpose register number, changing the architecture of the data processing device to more physical registers than the number of registers addressable by the instruction. Access without
The programs shown in Tables 7, 8, and 9 can be realized,
It is possible to prevent performance degradation due to waiting for instruction execution due to data reading and register collision, thereby enabling high-speed execution of a program.

In particular, as can be seen from the programs shown in Tables 7, 8, and 9, in the list vector operation in the vector calculation of the scientific and technical calculation in which the loop of the instruction sequence is mainly performed, each loop is used. In the source index type operation, the processing of the i-th element is performed by loading the list vector into the general-purpose register of the i-th element by the general-purpose register list load instruction in the (i-2) -th loop. And i-th data using the data in the general-purpose register as a main storage address.
"Source vector (vector to be read) by floating-point register reload instruction in -1 loop"
Of the element indicated by the i-th element of the list vector to the floating-point register, and the target vector (vector to be written) to the i-th element by the floating-point register post-store instruction in the (i + 1) -th loop. , By storing the data in the floating-point register, to load the list vector for one element number.
The distance in the instruction sequence of the processing of loading the source and source vectors to the load and target vectors is increased, and performance degradation due to the influence of the data read time can be prevented. In the target index type operation,
The processing of the i-th element is performed by loading the list vector into the general-purpose register of the i-th element by the general-purpose register reload instruction in the (i-2) -th loop and the floating-point register pre-load in the (i-1) -th loop. Loading a source vector (vector to be read) into the floating-point register of the i-th element by a load instruction, and data in the general-purpose register by a floating-point register list store instruction in the (i + 1) -th loop. By storing the data in the floating-point register in the “element indicated by the i-th element of the list vector” in the floating-point register using
Load of list vector for one element number, source
The distance on the instruction sequence of the load of the data vector and the processing of the store to the target vector on the instruction sequence is increased, and the performance can be prevented from deteriorating due to the influence of the data read time, and the speed can be increased. In the particle propulsion type operation, the processing of the i-th element is
Load the i-th element of the list vector to the general-purpose register by the general-purpose register reload instruction in the (i-2) -th loop, and execute the floating-point register reload instruction in the (i-1) -th loop. Loading one vector (ie, vector A in equation (3)) into the first floating-point register of the element indicated by the i-th element of the list vector, and the second vector (ie, the vector A by the floating-point register preload instruction) Loading the ith element of the vector B) of equation (3) into the second floating-point register, adding the value of the two floating-point registers by a floating-point addition instruction in the ith loop (i.e., The addition of the element indicated by the ith element of the list vector of the first vector and the ith element of the second vector), by the floating-point register list store instruction in the (i + 1) -th loop The serial addition result, the value of the general purpose register used in the main storage address "of the first vector,
By storing in the element indicated by the i-th element of the list vector, the loading of the list vector, the loading of the first vector, and the loading of the second vector (the loading of the first vector) for one element number are performed. Since the load and the load of the second vector have no correlation, they are performed in the same loop), the addition of the element of the first vector and the element of the second vector, and the first of the addition results.
The distance in the instruction sequence of the store processing to the vector is increased, and the performance can be prevented from being deteriorated due to the influence of the data reading time and the operation execution time, and the speed can be increased.

Here, an extended floating point preload instruction not shown in Tables 7, 8, and 9 is introduced in the embodiment.
This is because, in a system that takes a long time to read data from the main memory, as shown in the program of Table 8, the data loaded in the loop following the loop that issued the preload instruction. −
Even if an attempt is made to operate the data, there is a possibility that the load has not been completed yet and the operation instruction has to wait. Therefore, an extended floating-point preload instruction has been devised so that it can be programmed to operate the loaded data in the next loop following the loop that issued the preload instruction. .

[0162]

According to the present invention, by changing the current floating-point window pointer, a certain floating-point register number in an instruction is converted to a different physical floating-point register number. Some floating-point register numbers or general-purpose register numbers are converted to different physical general-purpose register numbers, so that more physical registers than the number of registers addressable by the instruction can be used without changing the architecture of the data processing device. Since access can be made, it is possible to prevent performance degradation due to data reading and waiting for instruction execution due to collision of a register, and it is possible to execute a program at high speed.

In particular, in the list vector operation in the vector calculation of the scientific and technical calculation in which the repetition of the loop of the instruction sequence is the main, the window used for each loop is changed, and in the source index type operation, i is used. The processing of the i-th element is
Loading the i-th element of the list vector into the general-purpose register by the general-purpose register list load instruction in the 2 loop;
The data in the general-purpose register is used as a main storage address,
Floating-point register restore in i-1 loop
Load of the source vector (the vector to be read) indicated by the i-th element of the list vector to the floating-point register, and the data by the floating-point post-store instruction in the (i + 1) -th loop. Loading of the list vector for one element number, by doing by storing the data in the floating point register to the ith element of the get vector (the vector to be written);
The distance on the instruction sequence of the processing of loading the source vector and storing it in the target vector becomes longer, and it is possible to prevent a decrease in performance due to the influence of the data reading time, thereby increasing the speed. In the target index type operation, the processing of the i-th element is performed by loading the list vector into the general-purpose register of the i-th element by the general register list load instruction in the (i-2) -th loop. Load a source vector (read vector) to the floating-point register of the i-th element by the floating-point register preload instruction in the i-1 loop, and store the floating-point register list in the i + 1-th loop The data in the floating-point register using the data in the general-purpose register by the instruction as the main storage address.
Of the target vector, the i-th of the list vector
By doing a store to "element indicated by element", load the list vector for one element number,
The distance on the instruction sequence of the processing of loading the source vector and storing it in the target vector becomes longer, and it is possible to prevent a decrease in performance due to the influence of the data reading time, thereby increasing the speed. In the particle propulsion type operation, the processing of the i-th element is performed by loading the list vector into the general-purpose register of the i-th element by the general-purpose register list load instruction in the (i-2) -th loop. Load the first vector (ie, vector A in equation (3)) by the floating point register list load instruction in one loop to the first floating point register of the element indicated by the ith element of the list vector. Loading the i-th element of the second vector (i.e., the vector B in equation (3)) into the second floating-point register by the floating-point register preload instruction, and adding the floating-point at the i-th loop. By order (I.e., the addition of the element indicated by the i-th element of the list vector of the first vector and the i-th element of the second vector) of the floating-point register list in the (i + 1) -th loop Using the value of the general-purpose register of the addition result by the store instruction as the main storage address,
By storing in the element indicated by the i-th element of the list vector, the loading of the list vector, the loading of the first vector, and the loading of the second vector (the loading of the first vector) for one element number are performed. Since the load and the load of the second vector have no correlation, they are performed in the same loop.) The addition of the first vector element and the second vector element, and the first
The distance in the instruction sequence of the store processing to the vector is increased, and the performance can be prevented from deteriorating due to the influence of the data read time and the operation execution time, and the speed can be increased.

[Brief description of the drawings]

FIG. 1 shows a logical floating-point register number according to the present invention.
One embodiment of physical floating point register number conversion.

FIG. 2 shows a logical floating-point register number according to the present invention.
One embodiment of physical general register number conversion and logical general register number-physical general register number conversion.

FIG. 3 shows data for executing the instruction shown in FIG. 4 according to the present invention.
FIG. 1 is a configuration diagram showing one embodiment of a data processing device.

FIG. 4 shows a current floating-point window pointer change instruction, a current general-purpose window pointer change instruction, a floating-point register preload instruction, an extended floating-point register preload instruction, a floating-point register post-store instruction, and a floating-point register reload instruction according to the present invention. FIG. 4 is a diagram showing an embodiment of an instruction format of a load instruction, a general-purpose register list load instruction, and a floating-point register list store instruction.

[Explanation of symbols]

10 is an instruction processing unit, 20 is a storage control unit, 3
0 is a main memory, 101 is an instruction register, 102 is an instruction control unit, 103 is a general-purpose register group, 104 is a general-purpose operation unit, 105 is a physical floating-point register group, 106 is a floating-point operation unit, 107 is an address adder, 108 is a cache, 109 is a main memory access control unit, 110 is a current floating point window pointer register, 111 is a current window pointer valid register, 112 is a first conversion circuit,
113 is a current general-purpose window pointer register, 114 is a second conversion circuit, and 115 and 116 are signal lines

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Nakamura 4-1043 Namiki, Tsukuba, Ibaraki (72) Inventor Hiromitsu 2-23-6, Akumabo, Tsukuba, Ibaraki (72) Inventor Hideo Wada No. 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. Kanagawa Plant (56) References JP-A-61-267134 (JP, A) JP-A-61-241870 (JP, A) JP-A-61-136131 (JP) , A) JP-A-60-129838 (JP, A) Information Processing Society of Japan Research Report ARC91-8 p. 61-68 (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 17/16 G06F 9/38

Claims (3)

(57) [Claims] An instruction is executed using a main memory for holding instructions and data, and main memory data held in the main memory.
The instruction includes reading main memory data from the main memory,
A load instruction to be stored in the register numbered in the instruction, a store instruction to store data from the register numbered in the instruction to the main memory, a register numbered in the main memory or the instruction Data is read from the memory, an operation is performed on the data, and an operation result is stored in a register numbered in the instruction. A register called a physical first register, a register called a current first window pointer register composed of a plurality of bits, and a register called a 1-bit current window pointer valid register, the number of which is larger than the number of registers of a first type called a first type register When the value of the current window pointer valid register is 1, the first register number in the instruction is changed to the physical first register. A first conversion circuit, which converts the number of the first registers into address numbers and changes the pattern of the conversion according to the value of the current first window pointer register; the number of the first registers addressable by an instruction; and the second register addressable by an instruction. When the value of the physical second register is larger than the number of registers of the second type called register, the register called current second window pointer register comprising a plurality of bits, and the value of the current window pointer valid register is 1, the instruction Converting the first register number or the second register number in the above into a physical second register number,
And pattern of the conversion by the current second window pointer register value - and a second converting circuit for changing the down, before
The instruction processing unit includes a current first window pointer change instruction for changing a value of the current first window pointer register, a current second window pointer change instruction for changing a value of the current second window pointer register, The second register number in the instruction is converted into a second number by the second conversion circuit using the value of the current second window pointer register.
The data is converted into a physical register, data is read from the main memory address stored in the second physical register indicated by the second physical register number, and the first register number in the instruction is replaced with the current first window pointer register. , But is different from the value of the current first window pointer register as the value of the current first window pointer register, and converted by the first conversion circuit into a physical first register number. A first register preload instruction for storing the data in the physical first register indicated by the first register number, and the first register number in the instruction is determined from the value of the current first window pointer register. A value different from the value of the first window pointer register is regarded as the value of the current first window pointer register, and the first conversion circuit determines the physical first register number. The data is read from the physical first register indicated by the physical first register number, and the second register number in the instruction is converted by the second conversion circuit using the value of the current second window pointer register. A first register post-store instruction for converting the data into a second physical register and storing the data at a main memory address stored in the second physical register indicated by the second physical register number; Is determined from the value of the current second window pointer register, but a value different from the value of the current second window pointer register is regarded as the value of the current second window pointer register. The data is read from the main memory address stored in the physical second register indicated by the physical second register number, and converted into the first number in the instruction. The register number is determined from the value of the current first window pointer register. However, a value different from the current first window pointer register is regarded as the value of the current first window pointer register, and the first conversion circuit performs the physical first A first register reload instruction for converting to a register number and storing the data in the physical first register indicated by the physical first register number;
The first second register number in the instruction is converted into a physical second register number by the second conversion circuit using the current second window pointer register, and the first second register number is stored in the physical second register indicated by the physical second register number. The main memory address is determined using the stored information, data is read from the main memory address, and the second second register number in the instruction is determined from the value of the current second window pointer register. However, a value different from the value of the current second window pointer register is regarded as the value of the current second window pointer register and is converted by the second conversion circuit into a physical second register number.
A second register reload instruction for storing the data in the physical second register indicated by the physical second register number, and the first register number in the instruction is determined from the value of the current first window pointer register. Considers a value different from the value of the current first window pointer register as the value of the current first window pointer register, converts the value into the physical first register number by the first conversion circuit, and indicates the physical first register number. The data is read from the physical first register, and the register number in the instruction is determined from the value of the current second window pointer register, but the value of the current second window pointer register is different from the value of the current second window pointer register. Assuming the value of the window pointer register, the second conversion circuit converts the value into the physical second register number, and the physical second register indicated by the physical second register number. The de in the main memory address stored in the data - has means for executing a first register list store instruction for storing data, said first register preload - de instruction, the first register poststore instruction, the first One register reload instruction, the second register reload instruction
In the execution of the load instruction, the store instruction, and the operation instruction except for the load instruction, the first register list store instruction, the first register number in the instruction is determined by using the value of the current first window pointer register. Physical 1st by 1 conversion circuit
The register is converted to a register number, the physical first register indicated by the physical first register number is referred to, and the second register number in the instruction is converted to the physical first register by the second conversion circuit using the value of the current second window pointer register. 2. A data processing device, wherein the data is converted into two register numbers and controlled so as to refer to the physical second register indicated by the physical second register number. 2. The data processing according to claim 1, wherein a register number in said first register list load instruction and said first register list store instruction is a first register number. apparatus. 3. The first register numbered in the instruction and the physical first register are dedicated registers for storing a floating-point number, which are called floating-point registers, and the first register numbered in the instruction. 2 registers and the physical second
2. The data processing apparatus according to claim 1, wherein the register is a general-purpose register called a general-purpose register for storing fixed-point numbers, logical data, binary integers, and the like.