JPS6314233A - Decimal multplying circuit - Google Patents

Abstract

PURPOSE:To decrease the number of times of addition and to improve multiplication speed by generating the multiple table of multipliers and performing the process of (one digit of multiple)X (multiplier) by one-time addition. CONSTITUTION:The table containing values which are 0-9 times as large as the multiplier is generated in a storage circuit K by specific processing. Then, a register E is set to 0 and a switching circuit F is shift3d by one digit to right; and the multiplicand is inputted to a multiplicand register I in a right-justified state and the circuit K is addressed with the least significant digit of the register I. The multiples of the multiplier which is addresses are inputted to a register H, the value in a register E is shifted by one digit to right through the switching circuit F and added to the value in a register H, and the result is inputted to the register E again. The least significant digit of the register E is put at the most significant digit of the register I simultaneously with the right one-digit shifting of the register I. The multiple of the multiplier addressed with the least significant digit of the register I is inputted to the register H and the arithmetic is repeated. This loop is executed as many times as the number of digits of the multiplicand to generate the high-order digit part of the product in the register E and the low-order digit part of the product at the high- order digit part of the register I.

Description

[Detailed Description of the Invention] [Overview] In order to speed up decimal multiplication, an electronic computer is configured to create a multiplier table and perform (1 digit of the multiplicand x multiplier) in one addition. This reduces the number of additions and increases the multiplication speed.

[Industrial Field of Application] The present invention relates to an arithmetic circuit for a computer, and particularly to a decimal multiplication circuit.

The calculation speed of a computer is directly related to the performance of the computer, and high speed is required. Since decimal multiplication is performed by expanding into decimal addition, it takes time, and a faster calculation method is desired.

[Conventional technology] Conventional decimal multiplication is performed as follows.

First, look at the least significant digit of the multiplicand and add that value to the multiplier to create a multiple of the multiplier and use it as the intermediate product.

Next, look at the next digit of the multiplicand, create a multiplier for that value, and use it as the intermediate multiplier. Shift the intermediate product one place to the right and add the intermediate multiplier to create a new intermediate product.

Next, look at the next digit of the multiplicand and create the intermediate product in the same way,
Repeat until the most significant digit of the multiplicand.

[Problems to be Solved by the Invention] Assuming that the average value of the values of each digit of the multiplicand is 4, the number of additions required for one multiplication is determined by the following equation.

Number of additions = number of digits in the multiplicand x 4-1 (however, the number of digits in the multiplier must be at least one digit less than the number of digits in the adder) For example, 10-digit multiplication requires 39 additions.

Therefore, according to the prior art, a large number of additions are required and a large amount of calculation time is required.

The present invention aims to provide a novel decimal multiplication circuit that can significantly reduce the number of additions compared to such conventional multiplication circuits.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of a decimal multiplication circuit according to the present invention.

In FIG. 1, A is an intermediate result register into which intermediate results are stored, B is a decimal adder, and C is a storage circuit into which multiples of multipliers are stored.

D is a multiplicand register, and the memory circuit C is addressed according to its contents.

The multiple of the multiplier addressed by multiplicand register D enters adder B, is added with the intermediate result from intermediate result register A, and is placed back into intermediate result register A.

[Operation] In the configuration shown in FIG. 1, regardless of whether each digit of the multiplicand stored in the multiplicand register D has any value from O to 9,
To find the intermediate product of each digit, only one addition is required for each digit.

The number of additions required for one multiplication is determined by the following equation.

Number of additions - 8 + number of digits of multiplicand - 1 In the above equation, "8" is the number of additions required to create the multiplier table.

[Example] The present invention will be described in more detail below with reference to Examples shown in FIGS. 2 and 3.

FIG. 2 is a circuit diagram of an embodiment of the present invention.

In FIG. 2, E is an intermediate result register into which intermediate results are stored, and F is a switching circuit for shifting the output of the intermediate result register E by one digit to the right or sending it as is.

G is a decimal adder, and H is a register that holds read data to the storage circuit.

K is a storage circuit into which multipliers from 0 times to 9 times are stored, and are addressed by the least significant digit or register of multiplicand register I.

■ is a multiplicand register into which the multiplicand is stored.

J is a one-digit right shift circuit.

L is a register whose contents are incremented by a +1 adder.

The operation of the circuit of this embodiment will be explained below.

(1) First, a multiple table of multipliers is created.

(11) Register E is set to "0" and the value of register E is output as is from switching circuit F.

(12) A multiplier is stored in register H, the memory circuit is addressed by a register, and the register is “0”.
It becomes.

(13) The output of register E is written to memory circuit K,
E+H is placed in register E, and 1 is added to L.

(14) By repeating the operation in (13) 10 times, the multipliers 0 to 9 times are stored in the memory circuit K at addresses 0 to 9.

(2) Next, a multiplication loop is performed.

(21) Register E is set to “0” and switching circuit F is set to right 1.
It is considered a digit shift.

(22) The multiplicand is stored in register (2) right-justified, and the storage circuit is addressed by the least significant digit of register (I).

(23) The multiple of the multiplier addressed by the least significant digit of register ■ enters register H, and the output of register E becomes F
It is shifted one digit to the right by , and is added to the output of register H, and the output is put into register E again.

(24) The least significant digit of register E is put into the most significant digit of register I at the same time as the output of register 2 is shifted by J by one digit to the right.

(25) Again, the multiple of the multiplier addressed by the least significant digit of register I enters register H, and the operation is repeated.

(26) If this loop is repeated for the number of digits of the multiplicand, the upper part of the product is generated in the register I, and the lower part of the product is generated in the upper part of the register I.

FIG. 3 is a diagram showing a comparison between the number of additions according to the present invention and the number of additions according to the conventional example.

As is clear from the figure, when the number of digits is small, the effect of reducing the number of additions is small because of the number of additions required to create a multiple table, but as the number of digits becomes large, the number of required additions is significantly reduced.

[Effects of the Invention] As explained above, according to the present invention, the number of additions can be significantly reduced compared to the conventional technology, and the multiplication speed can be improved, and the effect of contributing to the improvement of computer performance is extremely large. It is.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing a comparison of the number of additions between the present invention and a conventional example. In the drawings, A, D, E, H, I, and L are registers, B and G are adders, C is a storage circuit, F is a switching circuit, and J is a shift circuit, respectively. ffl block diagram of the present invention Fig. 1

Claims (1)

[Claims] An intermediate result register (A) that holds an intermediate result of multiplication; a storage circuit (C) that stores a multiple of a multiplier; and an output of the storage circuit (C) and storage of the intermediate result register (A). an adder (B) that performs decimal addition of the intermediate results and inputs the addition result to the intermediate result register (A); and a multiplicand register (D) that holds the multiplicand and addresses the storage circuit (C).
A multiple of the multiplier is stored in advance in the memory circuit (C), and 1
A decimal multiplication circuit characterized in that it is configured to perform (1 digit of multiplicand x multiplier) by adding times.