JPS6224365A - Product sum arithmetic unit - Google Patents

Abstract

PURPOSE:To attain a product sum operation at a high speed with a small number of circuit elements by dividing the result of multiplication into plural blocks and carrying out addition for each block. CONSTITUTION:A multiplicand Xi and a multiplier Yi are given from input registers 10 and 11 and the multiplication is performed by a multiplier 12. The upper and lower parts of the result of this multiplication are supplied to an adder circuit 13 and a register 16 respectively. The circuit 13 adds the lower part of the result of multiplication and the output C of a register 14 and supplies the result of this addition to the register 14. A latch circuit 15 fives the output D of '0' and '1' to an adder circuit 17 with absence and presence of a carry of the circuit 13 respectively. The register 16 stores temporarily the upper part of the result of the multiplier 12 and gives the output E to the circuit 17. The output of the circuit 17 is given to a register 18 and the output F of the register 18 is supplied again to the circuit 17. Thus the circuit 17 performs the addition among the upper bits of the result of multiplication, the output F and the latch output D and stores the result of this addition into the register 18. The cumulative product sum operation is possible by joining both registers 14 and 18 together.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a product-sum calculator used in digital signal processing that is high-speed and has a small number of circuit elements.

(Conventional technology) Conventional technology in this field is as follows. ``Computera
(1979), John
John Wiley & Sons
& 5ons, Inc.) (US) P, 84-91.

In this document, a CLA that performs high-speed addition operations is used.
(carry look ahead) adder circuit is described. A CLA adder circuit is, for example, an adder circuit that is composed of multiple full adders, etc., and a carry-look-ahead generator that only performs carry (carry). By doing this, high-speed calculations can be performed.

FIG. 2 is a block diagram showing an example of the configuration of a conventional product-sum calculator using this CLA adder circuit. This product-sum calculator has input registers 1 and 2, multiplier 3, register 4, CL
It includes an A addition circuit 5 and a register 6.

Here, the input register 1 is a register that temporarily stores the wave product aXi, and the input register 2 is a register that temporarily stores the multiplier Yi. Multiplier 3 multiplies multiplicand Xi by multiplier Yi. Register 4 receives the operation result of multiplier 3 Xi・
Store Yi. The CLA addition circuit 5 performs a CLA addition operation from the contents of the register 4 and the contents of the register 6. The register 6 stores the operation result of the GLA addition circuit 5.

The operation of the product-sum calculator configured as described above will be explained.

First, the wave fiX1 is input to the input register 1, and the wave aY! is input to the input register 2. When is input, the multiplier 3 multiplies the wave power aL by the multiplier Y1. This calculation result x1·Yl is stored in the register 4. The CLA addition circuit 5 adds the contents of register 4 and the contents of register 6, but since register 6 is cleared at the time of initialization, this CLA addition circuit 5 adds the contents of register 4 and the contents of register 6.
・Add Yl and the contents O of register 6. This addition result XI-Yl-0=Xi.Yl is stored in the register 6.

Next, when the multiplicand x2 is input to the manual register l and the power fiY2 is input to the input register 2, the multiplier 3
The calculation of Y2 is performed, and the calculation result x2·Y2 is stored in the register 4. The CLA adder circuit 5 calculates the contents X2 and Y2 of the register 4 and the contents X! of the register 6. - Addition with Yl is performed, and the result of this addition, Xi.Yl+X2.Y2, is stored in the register 6.

By performing the same processing below, register 6 contains: 3
Xi-Yi is stored, and the cumulative product-sum operation is performed in this manner.

(Problems to be Solved by the Invention) However, in the product-sum calculator with the above configuration, the CLA adder circuit 5 has a carry-ruth-ahead generator in addition to a normal adder. There was a problem that a large number of circuit elements were required.

The present invention provides a product-sum calculator that solves the problem of the prior art, which is that the number of circuit elements is large.

(Means for Solving the Problem) In order to solve the problem, the present invention provides a product-sum calculator that multiplies a multiplicand Xi by a multiplier Yi and sequentially accumulates the multiplication results Xi and Yi. Divide the multiplication results Xi and Yi into multiple blocks, and multiply the multiplication results X in each block.
In addition to providing a plurality of adder circuits that sequentially add i and Yi, latching the carry output of the lower adder circuit among these adder circuits, and using the carry output to perform the addition operation of the higher order adder during the addition operation in the upper adder circuit. A plurality of latch circuits are provided for input to the circuit.

(Function) According to the present invention, since the product-sum calculator is configured as described above, the jM number of adder circuits respectively add the multiplication results in the divided blocks. The latch circuit latches the carry output from the lower-order adder circuit, and manually outputs the carry output to the higher-order adder circuit. Therefore, the upper adder circuit adds the lower carry output and the multiplication results in the divided blocks, which allows the so-called multi-stage pipeline accumulation operation to
This makes it possible to perform high-speed cumulative product-sum operations with a small number of circuit elements. Therefore, the above problem can be eliminated.

(Embodiment) FIG. 1 is a block diagram of a product-sum calculator showing an embodiment of the present invention.

In FIG. 1, 10.11 is an input register, and the output terminals of the input registers to and tt are connected to the input terminal of the multiplier 12. One of the two output terminals of the multiplier I2 is connected to an adder circuit 13 and a digital summator 14, and further connected to the adder circuit 13 is a latch circuit 15 for 1-bit carry. Further, the other output terminal of the multiplier 12 has a register IEI.

An adder circuit 17 and a register 18 are connected, and the adder circuit 17 is further connected to the latch circuit 15.

Here, the input register IO is a circuit that temporarily stores the multiplicand Xi and provides its output A to the multiplier 12. Similarly, the input register 11 temporarily stores the multiplier Yi and outputs its output B to the multiplier! This is the circuit that connects to the second stage.

The multiplier 12 is a circuit that multiplies the multiplicand Xi by the multiplier aYi.The operation result of this multiplier 12 is 1. For example, if the operation result is 8 bits, the lower 4 bits are input to the addition circuit 13, and the upper 4 bits are input to the adder circuit 13. The bit is input into register 16.

The adder circuit 13 has its output given to the register 14,
Further, the output C of the register 14 is inputted again to this circuit, and the lower 4 bits of the operation result of the multiplier 12 are added to the register output C. Register 14 is adder circuit 1
This is a circuit that stores the calculation results of step 3. The rough child circuit 15 connected to the adder circuit 13 latches the carry of the adder circuit 13, and outputs "0" when there is no carry in the adder circuit 13, and "1" when there is a carry. can be enjoyed by the adder circuit 17.

The register 16 is a circuit that temporarily stores the upper 4 bits of the operation result of the multiplier 12, and its output E is provided to the adder circuit 17. The adder circuit 17 is a circuit whose output is given to the register 18, and further inputs the output F of the register 18 again.The six registers 18 that perform addition of the upper 4 bits, the register output F, and the latch output are Addition circuit 1
This is a circuit that stores the calculation result of step 7.

Next, the operation will be explained by taking as an example the case where the sum of products and sums calculation unit is used to perform the calculation of 10X 11+IOX 12=230.

Here, 10 (to > = 1010 (2) 11 (101 = 1 [1 (2) 12 (10) = ILOOr2). However, the subscript (10) represents a decimal number, and (2) represents a binary number. ing.

First, “1010” (=10
) is input, and “1011” is input to the other input register 11.
When (=11) is input, the 1 multiplier 12 performs the multiplication of 1010X 1011="01101110". The lower 4 bits “1110” are input to the adder circuit 13, and the upper 4 bits “0”
110"" is stored in register 16.

The adder circuit 13 adds the input data "1110" and the contents of the register 14, but since the register 14 is cleared at the time of initialization, the result of the addition is "1".
110'' and this is stored in the register 14.

On the other hand, the adder circuit 17 adds the contents of the register 16, the contents of the register 18, and the contents of the latch circuit 15.
Since the latch circuit 15 and the register 18 are initially cleared, the result of the addition is "03lO°", which is stored in the register 18.

Next, °"1010" (=10) is input to the input register 10, and "1110"' (=1
2-) is input, the multiplier 12 performs the multiplication of 1010X 1110="01111000". The lower 4 bits “+000” are input to the adder circuit 13, and the upper 4 bits “01”
11'' is stored in register 16.

The adder circuit 13 adds the input data "1000" and the content "1110" of the register 14. In this operation, digits are carried out to become "'10110", and the 1 bit carried out is latched by the latch circuit 15, and the lower 4 pins "'0110°" are stored in the register 14.

On the other hand, the adder circuit 17 calculates the contents of the register 16 '0111
'', the contents of the register 18, “0110”, and the contents of the latch circuit 15, “1”, are added, so the result of this addition is “1110”, which is stored in the register 18.

By the above operation, the lower 4 of the operation results are stored in the register 14.
Since the old PID is stored and the upper 4 bits of the operation result "1110" are stored in the register 18,
The sum of both results in 11100110''=230, and the correct calculation is performed.

FIG. 3 is a time chart showing each output A-F type IE of the circuit of FIG. Note that FIG. 3 (a) shows the calculation cycle.

In the calculation cycle M1, the input outputs A and B of the input register 10.11 are sent to the multiplier 12! When the outputs A and B are added by the multiplier 12, the lower bits of the multiplication result and the contents of the register I4 are added by the adder circuit 13 (FIG. 3(b)).

In the calculation cycle M2, the calculation result of the adder circuit 13 is stored in the register 14, and the contents of this register 14 are given to the adder circuit 13 as output C (Fig. 3 (C)).
). At the same time, the l-bit carry of the adder circuit 13 is latched by the latch circuit 15, and its output is sent to the adder circuit 17 (FIG. 3(d)). Furthermore, in this arithmetic cycle M2, the result of the multiplication performed in the previous arithmetic cycle is stored in the register 16, and the output E is given to the adder circuit 17. An addition is performed between the contents and the output of the latch circuit.

In the calculation cycle old, the calculation result performed by the adder circuit 17 in the calculation cycle M2 is stored in the register 18, and its output F is sent out (FIG. 3(f)).

The above operations are continuously repeated, and the product-sum operation results are stored in register 14 and register 18 one after another.

In this embodiment, since the two adder circuits 13 and 17 and the latch circuit 15 for 1-bit carry are provided, so-called pipeline operation is possible, and the addition speed is approximately doubled. Therefore, if the adder circuits 13 and 15 are configured with a ripple fist carry type etc. with a small number of circuit elements without requiring a high-speed CLA adder circuit, the number of circuit elements in the adder part can be reduced to about 1/2. This makes it possible to perform high-speed product-sum calculations. Therefore, it can be applied to various circuits such as voice recognition circuits in the field of digital signal processing.

In the embodiment described in L, two adder circuits 13 and 17 are provided, but three or more N adder circuits and a corresponding number of 1-bit carry latch circuits are provided to convert the multiplication result to N. Furthermore, the number of bits of the multiplier 12, the adder circuit 13.17, and the registers 10, 11, 14, 18, and 18 are limited to those described in the embodiment. Of course, this is not the case.

The present invention can also be applied to an arithmetic circuit that simply adds two input data.

(Effects of the Invention) As explained in detail, according to the present invention, the multiplication result is divided into a plurality of blocks and addition is performed for each block, so that high performance can be achieved with a small number of elements. The effect of being able to perform product-sum calculations of speed can be expected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of a product-sum calculator showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional product-sum calculator, and FIG. 3 is a time diagram for explaining the operation of FIG. It is a chart. to, 11... Input register, 12...
・Multiplication=. 13.17... Addition circuit, 14.16.18.
...Register, 15...Latch circuit. □ Multiply-sum calculator of the present invention (Figure 1) Conventional unit 8] Calculator unit (Figure 2) Operation time of Figure 1 (Figure 3)

Claims (1)

[Claims] The multiplicand Xi is multiplied by the multiplier Yi, and the multiplication result Xi・
In a product-sum calculator that sequentially accumulates Yi, the multiplication results Xi and Yi are divided into a plurality of blocks, and a plurality of adder circuits that sequentially add the multiplication results Xi and Yi in each block; and these adder circuits. A sum of products characterized by comprising a plurality of latch circuits that latch the carry output of the lower adder circuit and input the carry output to the higher adder circuit during the addition operation in the higher adder circuit. Arithmetic unit.