JPH04205525A - Multiplier applying pipeline system - Google Patents

Abstract

PURPOSE:To improve the computing speed by minimizing the worst path at each stage for transmission of the carries. CONSTITUTION:The latch registers 56-59 of more significant bits of a multiplicand X are provided at the positions closer to the input side of the multiplicand X than the latch registers 50-55 of less significant bits of the multiplicand X. The registers 50-59 latch the computing results at the stages of less computing frequencies at the more significant bit side where much time is needed for transmission of carries. Thus it is possible to shorten the carry transmission lines of the worst paths set at both more and less significant sides. Then the computing time is shortened in a pipeline system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplier using a pipeline system, and particularly to improvement of a carry propagation bus in each stage.

[Prior Art] FIG. 2 is an example of a multiplier using a conventional pipeline method, and is a circuit diagram of a multiplier with an operation bit length of 4×4 using the pipeline method.

In the figure, a multiplier with an operation bit length of 4×4 using the conventional pipeline system has input terminals 100 to 100 for the multiplicand Xn.
103, multiplication number Yn input terminals 200-203, multiplication adder (MUL) 10-13°20-23.30-33.
40-43, latch registers 50-61, and multiplication result output terminals 300-307.

As is clear from the figure, the latch registers 50 to 59 of the multiplier using the conventional pipeline method are inserted between the second and third digits of the multiplication number, and this allows the multiplier to move up and down. It is divided.

Next, the operation of this conventional multiplier will be explained.

For example, multiplication with arithmetic bit length of 4×4 (multiplicand
01(13), multiplication number Y-1011), the calculation is performed as follows.

(The following is a margin) It is obtained as ×1011. As can be seen from the above calculation formula, the result of multiplication of a 4-digit number is a 2×4−8-digit value.

When this operation is performed by a computer, the above method is further decomposed to obtain the partial products of each stage, and the results are used to perform an addition operation.

That is, for each digit of the multiplicand X, the number is set to X3. X2, Xi
, XO (1101), and the number Y3 . for each digit of the multiplication number Y.
Y2. When Yl, YO (1011), this calculation is performed as follows.

In the first stage MULIO-13, YO·X and the initial value 0000 are added.

lXll0I(YO・X)-1101 +oooo.

1101 . . . Partial product 1 In the second stage MULs 20 to 23, Yl −X shifted by one digit to the left and partial product 1 are added.

1xl101 (Yl-X)-1101+ 1101 100111... Partial product 2 In the third stage MULs 3o to 33, Y2-X shifted by one digit to the left and partial product 2 are added.

1xl101 (Y2-X)-0000000C1s* +100111 100111...Partial product 3 In the fourth stage MUL4o to 43, Y3-X shifted one digit to the left and partial product 3 are added.

lXll0I(Y3 ・X)-11011101**
* + 100111 10001111...Solution In this way, with the conventional multiplier shown in FIG.
A solution for multiplication of 4×4 bit length data can be obtained.

The multiplier using the pipeline method has latch registers 50 to 61 in order to perform pipeline processing, and in these latch registers 50 to 61, the result of partial product n(n-2), etc. The data is latched so that multiplication operations can be performed on different data on the upper and lower sides to increase the calculation speed.

That is, in FIG. 2, latch registers 50 to 55
latches the result of partial product 2 (including the carry bit latch register 55), latch registers 56 to 59 latch the input data of input terminals 100 to 103 of the multiplicand X, and latch registers 60 and 61 Input data at the Yn input terminals 202 and 203 is latched to enable calculations on different data in the MULs at the front and rear stages.

Since the calculation time is determined by the time it takes for the carry in the lower bits to propagate to the most significant bit, the pipeline method that provides such a latch register makes it possible to perform the next operation during the propagation of the carry. Computation time can be reduced.

As shown in Fig. 3, the MUL consists of an AND circuit A and an adder (full adder) B, and in the AND circuit A, 1 bit Xi of the multiplicand and 1 bit Yi of the multiplier
, and in adder B, the result of AND circuit A is
The data Sl of the corresponding bits of the partial product and the carry CI from the lower MUL are added, and the operation results SO and carry CO are output.

[Problems to be Solved by the Invention] However, the latch registers of multipliers using the conventional pipeline method are inserted horizontally and divide the multiplier into upper and lower parts, so carry propagation in the multiplier in Figure 2 The worst path (longest path) is the MUL
There are 6 MULs of IO~11-12-13-22-23, and the calculation time for one stage is 6 MULs. On the other hand, the calculation time is desirable to be short, and there has been a desire to further reduce the calculation time.

The present invention has been made in view of the above problems, and an object of the present invention is to obtain a multiplier using a pipeline system that can reduce the worst path of carry propagation.

[Means for Solving the Problems] In order to achieve the above object, a multiplier using a pipeline system according to the present invention has a method in which a latch register on the upper bit side of the multiplicand is compared with a latch register on the lower bit side. It is characterized by being placed near the input side of the multiplicand.

[Operations] Therefore, according to the multiplier using the pipeline method of the present invention, the latch register latches the operation result at the stage where the number of operations is small on the upper bit side where carry propagation takes time. As a result, the carry propagation path in the worst path on the upper side and the lower side can be shortened, and the calculation time in the pipeline system can be shortened.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of a multiplier using the pipeline system of the present invention, and shows an operation bit length of 4 in the two-stage pipeline system.
FIG. 2 is a circuit diagram of an unsigned multiplier of X4.

In the figure, a multiplier with an operation bit length of 4×4 using the pipeline system of the present invention has an input terminal 100 for a multiplicand X.
~103, input terminals 200 to 203 of the multiplication number Y, and M
ULIO~13.20~23.30~33.40~43
, latch registers 50 to 63, and multiplication result output terminal 3
It consists of 00 to 307.

These components are similar to conventional pipelined multipliers, but with latch registers 50 to 6.
3 is different from the conventional one, and is inserted in the direction from the most significant multiplicand X3 bit position to the most significant multiplicand Y3 bit position, that is, in the diagonal direction from the upper left to the lower right in the figure.

For this reason, in the multiplier of this embodiment, the latch registers 50 to 55 do not latch the result of partial product 2, but rather the value in the middle of calculation of partial product 2 and the value in the middle of calculation of partial product 3. It will latch.

Therefore, the most significant bit X3 of the multiplicand X and the multiplier Y
The multiplication of the second bit Y1 in the MUL 23 is not performed in the previous stage, but the multiplication of the least significant bit XO of the multiplicand X in the MUL 30 by the third bit Y2 of the multiplier is performed in the previous stage.

Therefore, the value in the middle of calculation of partial product 2 is latched in latch registers 50 to 55, the input data of multiplicand is latched, and the multiplication number Yn is stored in the latch registers 61 to 63.
Input data at input terminals 201-203 is latched.

Then, the latch register causes the calculations after the multiplication of the most significant multiplicand X3 and the multiplier Y3 by the MUL 23 to be performed successively in the subsequent stage.

Therefore, if the vertical and horizontal carry propagation speeds of the MUL are equal, the worst path for carry propagation is the MUL10-11-12-1
5MUL of 3 to 22, and MUL in the latter stage pipeline
It becomes 5 MUL of UL23-32-41-42-43.

Therefore, the 6M multiplier using the conventional pipeline method
Compared to UL, the route can be shortened by 5 MUL, and the calculation time can be reduced by 1/6 to 17%.

[Effects of the Invention] As explained above, according to the multiplier using the pipeline system of the present invention, the worst path of carry propagation in each stage is minimized, so the calculation speed is significantly improved. It has the effect of being able to do something.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a multiplier using the Vibration system, showing an embodiment of the present invention; Fig. 2 is a block diagram of a multiplier using the conventional Vibration system; Fig. 3 is a block diagram of a multiplier using the Vibration system. FIG. 2 is a block diagram showing the configuration of MUL. 10~43...MUL 50~63...Latch register

Claims (1)

[Scope of Claims] A pipeline in which multipliers and adders whose number corresponds to the number of digits of a multiplicand and a multiplier are arranged in a matrix, and a latch register that latches intermediate calculation result data for each digit is provided inside the arrangement. A multiplier using a pipeline method, which is characterized in that a latch register on the upper bit side of the multiplicand is placed closer to the input side of the multiplicand than a latch register on the lower bit side. Multiplier used.