JPH04241623A - Decimal multiplication processor - Google Patents

Abstract

PURPOSE:To eliminate the need for data holding operations in a chip so as to improve the processing speed without performing a firmware branching process and multiple mode setting process by means of firmware. CONSTITUTION:The 1-9 times multiples of multiplicand data are generated by means of a multiple generating means 5 and stored in a multiple storing means 6 in corresponding to the multiples. On the other hand, the stored multiples are read out and sent to an adder 2 for arithmetic operations by successively fetching multiplier digits from the high-order digit of multiplier data stored in a multiplier holding register 7 and generating addresses to be read out from the means 6 by means of a multiple reading-out address designating means 9.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decimal multiplication processing device, and more particularly to a decimal multiplication processing device for multiplication of decimal data by an electronic computer.

0002

[Prior Art] Conventionally, this type of decimal multiplication processing device has
As shown in the flowchart of the multiplication process in FIG. 6, the multiplier digits are extracted one by one from the multiplier data (steps 301 to 3
04), performs firmware branching according to the extracted multiplier digit (step 305), sets a multiple mode by firmware at the firmware branch destination (step 306), and generates a multiple according to the set multiple mode (step 307). , after adding the generated multiple to the intermediate result of multiplication (step 308), perform a left shift by one digit (steps 309, 310), and return to step 304. When there are no more multiplier digits, the intermediate result is stored in memory. (step 311).

FIG. 5 is a typical block diagram for implementing the process shown in FIG. The block diagram in Figure 5 is 15 digits x 15
It is assumed that multiplication is performed within digits, and the arithmetic processing unit 30 includes an adder 1 that performs calculations between 16-digit data.
, 2 and 16 digits of data in units of 1 digit.

Now, when multiplicand data within 15 digits and multiplier data are sent from the memory, the multiplicand data becomes input data to the multiple generation means 5 and is used for multiple generation. On the other hand, the multiplier data is stored in the multiplier holding register 7, and the multiplier digits are extracted from the upper digits into the register 19 by the multiplier digit extracting means 8. The multiplier digit taken out in the register 19 is input to the branch address generation logic 32 in the firmware control section 31. The branch address generation logic 32 creates a branch address according to the input multiplier digits and sends it to the address register 33. Then, according to the branch address stored in address register 33, the microinstruction in control store 34 is read out and stored in control store register 35. A part of the microinstructions stored in the control store register 35 is stored in the multiple mode register 20 in the arithmetic processing unit 30. According to the contents of the multiple mode register 20, the multiple generating means 5 generates a multiple of the multiplicand and stores it in the adder input register 11. Next, the adder 2 and the adder input register 12 hold the lower 16 digits of the intermediate result of the multiplication. If this addition results in a carry, the adder 1 adds the carry to the adder input register 10 that holds the upper 16 digits of the intermediate multiplication result. The addition results of adders 1 and 2 are stored in adder output registers 13 and 14, respectively. Then, shifters 3 and 4 each shift the signal to the left by one digit, and the shift results are stored in shifter output registers 15 and 16. The data stored in shifter output registers 15 and 16 is stored in adder input registers 10 and 12, respectively, and added again with the multiple of the multiplicand data. The above operation is repeated, and when the extraction of the multiplier digit of the multiplier data stored in the multiplier holding register 7 is completed, the multiplication is completed. The contents of adder output registers 13 and 14 are then stored in memory as a product.

[0005]

[Problem to be Solved by the Invention] Despite recent advances in technology, RA
Data read from M must be held once in a register due to delay time constraints. These data are held in registers and then sent to each LSI chip.

In the conventional decimal multiplication processing method described above,
Extracts the multiplier digits one by one from the multiplier data, performs firmware branching according to the number of extracted digits, sets the multiple mode by firmware at the firmware branch destination, generates a multiple according to the set multiple mode, and calculates the generated multiple. Since the method is to perform a one-digit shift after adding to the intermediate result of multiplication, the process of performing firmware branching according to the extracted multiplier digit, and the process of setting the multiple mode by firmware at the firmware branch destination, are performed separately. The transfer of data to the RAM chip is always performed through the step of holding the data once in the RAM chip as described above, which has the drawback of consuming extra execution machine cycle time. Furthermore, since this drawback occurs during multiplication loop processing, there is a problem in that as the number of digits in multiplication increases, the execution machine cycle time for multiplication processing increases dramatically.

[0007]

[Means for Solving the Problems] A decimal multiplication processing device of the present invention has a decimal multiplication processing device having an adder and a shifter for processing data in decimal format, and includes: multiple generation means for generating a multiple of a multiplicand; a multiple storage means for storing the multiples generated by the multiple generation means in correspondence with multiples; a multiplier digit extraction means for extracting a multiplier composed of multiple digits one by one after storing the multiple in the multiple storage means; Multiple read address designation means for specifying the address of the multiple stored in the multiple storage means from the multiplier digit taken out by the multiplier digit extraction means and reading out the multiple stored in the multiple storage means and sending it to the adder. In a decimal multiplication processing device comprising an adder and a shifter for processing data in decimal format, a multiplier digit extraction means for extracting a multiplier digit composed of a plurality of digits one by one; A multiple mode setting means for setting a multiple mode from the multiplier digit extracted by the digit extraction means, and a multiple generation means for generating a multiple of the multiplicand according to the multiple mode set by the multiple mode setting means and sending it to the adder. It is constituted by having.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The embodiment in FIG. 1 assumes multiplication within 15 digits,
Adders 1, 2 and 16 that perform calculations between 16-digit data
A shifter 3 that performs a shift operation between digit data in units of digits,
4 is provided. Furthermore, 1 to 9 of the 15-digit data
A multiple generation means 5 for generating a multiple and a multiple storage means 6 for storing the multiple generated by the multiple generation means 5 are provided, and a multiplier holding register is provided to read the multiple stored in the multiple storage means 6. 7. A multiplier digit extraction means 8 and a multiple read address designation means 9 are provided. Further, the adders 1 and 2, shifters 3 and 4, and their input/output registers are constructed in the same manner as the conventional multiplication processing device shown in FIG.

FIG. 2 is a flowchart of the processing of the embodiment of FIG. 1, and the operation of FIG. 1 will be explained below with reference to FIG. When multiplicand data within 15 digits and multiplier data are sent from the memory, the multiplicand data becomes input data to the multiple generation means 5 (step 102) and is used for multiple generation. 1 generated by multiple generation means 5
The multiples of .about.9 times are stored in the multiple storage means 6 one after another. On the other hand, the multiplier data is stored in the multiplier holding register 7 (step 101), and from the multiplier data stored in the multiplier holding register 7, the multiplier digits are extracted from the upper digits by the multiplier digit extracting means 8, and the extracted multiplier digits are It is sent to the multiple read address designating means 9 (step 105). The multiple read addressing means 9 provides the read address of the multiple stored in the multiple storage means 6 and reads the multiple from the multiple storage means 6 (step 106). The read multiple is stored in the adder input register 11, and the lower one of the intermediate results of multiplication is stored in the adder input register 11.
It is added by adder input register 12 and adder 2 which hold 6 digits. If this addition results in a carry,
The adder 4 adds the result to the adder input register 10 that holds the upper 16 digits of the multiplication result. The addition results of adders 1 and 2 are added to adder output registers 13 and 14, respectively.
(step 107). If the extraction of the multiplier digit is not completed (step 108), the contents of adder output registers 13 and 14 are transferred to shifters 3 and 4.
are shifted to the left by one digit (step 109), and the shift results are stored in shifter output registers 15 and 16. The data stored in shift output registers 15 and 16 is stored in adder input registers 10 and 12, respectively, and added again with the multiple of the multiplicand data. Next, the process returns to step 105 and the operations of steps 106 to 109 are repeated, and when the extraction of the multiplier digit of the multiplier data stored in the multiplier holding register 7 is completed (step 10
8), the multiplication is completed and the adder output registers 13 and 1
4 is stored in memory as a product (step 11
0).

FIG. 3 is a block diagram of another embodiment of the invention. The embodiment in FIG. 3 assumes multiplication within 15 digits as in the case of FIG.
Shifters 3 and 4 that perform a digit-by-digit shift operation and their input/output registers are provided. Furthermore, a multiplier holding register 7 that holds 15-digit multiplier data, a multiplier digit extraction means 8, a multiple mode setting means 18 that outputs a multiple generation mode based on the extracted multiplier digit, and a multiplicand holding register 17
A multiple generating means 5 for generating a multiple of the multiplicand is provided.

FIG. 4 is a flowchart of the processing of the embodiment of FIG. 3, and the operation of FIG. 3 will be explained below with reference to FIG. When multiplicand data and multiplier data within 15 digits are sent from the memory, they are stored in the multiplicand data multiplicand holding register 17, become input data to the multiple generation means 5 (step 202), and are used for multiple generation. On the other hand, the multiplier data is stored in the multiplier holding register 7 (
Step 201). From the multiplier data stored in the multiplier holding register 7, the multiplier digits are extracted from the most significant digits by the multiplier digit extracting means 8, and the extracted multiplier digits are sent to the multiple mode setting means 18 (step 204). The multiple mode setting means 18 specifies the multiple generation mode of the multiple generation means 5,
The multiple generating means 5 generates a multiple of the multiplicand according to the multiple mode setting means 10 (step 205). This multiple is stored in adder input register 11. Hereinafter, as in FIG. 1, addition is performed by the adder input register 12 and the adder 2, which hold the lower 16 digits of the intermediate multiplication result. If this addition results in a carry, the adder 3 adds the result to the adder input register 10 that holds the upper 16 digits of the intermediate result of the multiplication. The addition results of adders 1 and 2 are stored in adder output registers 13 and 14, respectively (step 206). If the extraction of the multiplier digit has not been completed (step 207), the contents of adder output registers 13 and 14 are shifted to the left by one digit in shifters 3 and 4, respectively (step 208), and the shift results are transferred to shifter output registers 15 and 14. 16. The data stored in shifter output registers 15 and 16 is stored in adder input registers 10 and 12, respectively, and added to the multiple of the multiplicand data. Next, the process returns to step 204 and the operations of steps 205 to 208 are repeated, and when the extraction of the multiplier digit of the multiplier data stored in the multiplier holding register 7 is completed (step 207), the multiplication is completed and the adder output register 13 and 14 are stored in memory as a product (step 209).

[0013]

As explained above, in the first embodiment of the present invention, a multiple of a multiplicand is generated by a multiple generation means, and the generated multiple is stored in a multiple storage means corresponding to the multiple.
In another embodiment, the multiplicand is stored in a register by having a multiple read addressing means for extracting a multiplier consisting of a plurality of digits one by one and specifying an address for reading out the multiple stored in the multiple storage means. By having a multiple generating means that takes out a multiplier consisting of multiple digits one by one, sets a multiple mode, and multiples the multiplicand according to the multiple mode, the RAM
When transferring data from an M chip to another LSI chip, the data must be held once in the RAM chip, which is the conventional process of branching the firmware according to the multiplier digit taken out, and the process of branching the firmware at the destination of the firmware branch. Since there is no need to perform processing to set the multiple mode, and no additional execution machine cycle time is required, there is an effect that quick arithmetic processing can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a flowchart of the embodiment of FIG. 1;

FIG. 3 is a block diagram of another embodiment of the invention.

FIG. 4 is a flowchart of the embodiment of FIG. 3;

FIG. 5 is a typical block diagram of a conventional decimal multiplication processing method.

FIG. 6 is a flowchart of the block diagram of FIG. 5;

[Explanation of symbols]

1, 2 Adder 3, 4 Shifter 5 Multiple generation means 6 Multiple storage means 7 Multiplier holding register 8 Multiplier digit extraction means 9 Multiple read address specification means 10, 11, 1
2 Adder input registers 13, 14 Adder output registers 15, 16 Shifter output register 17 Multiplicand holding register 18 Multiple mode setting means 19 Register 20 Multiple mode register 30 Arithmetic processing unit 31 Firmware control unit 32 Branch address generation logic 33 Address register 34 Control store

Claims (2)

[Claims] Claims: 1. A decimal multiplication processing device having an adder and a shifter for processing data in decimal format, comprising: multiple generation means for generating a multiple of a multiplicand; and multiples generated by the multiple generation means are stored in correspondence with the multiples. a multiplier storage means for storing a multiple, a multiplier digit extraction means for extracting a multiplier consisting of a plurality of digits one by one after storing the multiple in the multiple storage means; A decimal multiplication processing device comprising: multiple reading address designating means for specifying the address of the multiple stored in the storage means, reading out the multiple stored in the multiple storage means and sending it to an adder. 2. A decimal multiplication processing device having an adder and a shifter for processing data in decimal format, comprising: multiplier digit extraction means for extracting a multiplier digit consisting of a plurality of digits one by one; It is characterized by having a multiple mode setting means for setting a multiple mode from the extracted multiplier digit, and a multiple generation means for generating a multiple of the multiplicand according to the multiple mode set by the multiple mode setting means and sending it to the adder. A decimal multiplication processing device.