SU1238072A2 - Device for generating memory address - Google Patents

Abstract

This invention relates to the field of computing. The purpose of the invention is to increase the speed. The device contains an address decoder, a transition comaid decoder, two registers, a trigger, a delay element, elements I and SH, and to achieve the goal, the additional element SH, two elements NOT, a trigger, one-shot, and a third register with the corresponding connections are entered. The invention can be used to create microprocessor systems with a large amount of memory, as well as microprocessor graphic information display systems. 1 il. i O) 1C 00 00 lN9

Description

The invention relates to computing and can be used to create microprocessor systems with a large memory capacity, as well as microprocessor-based graphic information display systems.

The purpose of the invention is to increase the speed.

The drawing shows the functional diagram of the device.

The device contains output 1 lower order address bits of the device, decoder 2 addresses, input 3 lower order address bits of the device, information. device 4 input, descrambler 5 transition commands, registers 6,7 and 3, output 9 most significant bits of the device address, element OR 10, trigger 11, delay element 12, element 13, element OR 14, trigger 15, element 16 , NOT element 17, one-shot 18, inputs 19 of the information record feature 20, device information read attribute, device address output 21, input 22 sign of transfer to another device memory cube, NOT element 23, inputs 24 characters of the high-order device bits, 25 device reset, inputs And outputs 26 - 36 devices.

The device works as follows.

The decoder 5 selects the commands given in table. 1. It is assumed that the address space of the memory block is divided into sections (cubes), each of which can be addressed by means of lower-order address bits.

A device can operate in two modes: software transition from the address space of one cube to another, and fast transfer of information from one cube to another, while software is in the same memory cube.

The mode is selected by the decoder 5 transition commands, since with the appearance of the first three commands (see table), the first three outputs of the decoder 5, and hence the output 26 of the first element OR 10 10 DEVELOPED 1, which corresponds to the first mode, and when the fourth and fifth commands appear on the data bus (see Table 1) on the corresponding outputs of the decoder 5 and the output 27 of the second

2380722

 element OR 14 on Wits 1, which corresponds to the second mode.

First Mode When the microcomputer is powered on or to re-start 5, the micro-computer generates a reset signal 25, which sets the registers 6, -7 and 8 to the zero state. At the same time, a zero starting address is set at input 3, and a zero address at output 10 9 is also set. Thus, when the microcomputer is started, it starts the execution of the program recorded in the first memory cube, the address of the computer

45

50

sixteen

one is 00.

15 The program transition is implemented when the first commands from Table 2 appear on the data bus. one.

Table 2 shows the transition process using the example of a program fragment.

20 from O cube to N cube and back.

To go from cube 00. to ON it is necessary to write the code ON into a microprocessor battery (A) in a certain place of the main program

25 at the command MU1 (or another) and output the contents of A to register 6 with the address Z at the command OUT (see Table 2 addresses XXXX - XX42). At the same time, when executing an OUT command, the microprocessor (the MP) reads the command in the first busbar cycle, reads the address in the second, and issues it as an input in the third. 3 is address Z, input 4 is ON code, and input 24 is an I / O Write signal, while at the first output of the address decoder 2 by matching the I / O Record 24 signal and Z code at input 3 appears 1 - 30 , on the leading edge of which, code 6 is written to register 6. When the next CALL ADDR command is executed, in the first machine cycle the MP reads the CALL-CD command code from input 4, and the same code goes to the input of the decoder 5 transition commands and by coincidence with the signal the first machine cycle Ml input 22 on the first output of the decoder 5 is Vits positive pulse, which, through the element IL 10 enters input 26 of the first trigger 11 and, on the falling edge, sets the trigger to I, which is delayed (at element 12) longer than the onset time of the second machine cycle, enters input 28 of element 13 and 13, in the 55 cycles of the CALL PM command executed em their staff duties. With the arrival of any next command to the second input of the element And 13 on the input

If2 of the first machine cycle will also stop 1, which will pass through I and 13 and, on line 29. the trigger 11 on O will drop its front edge and write the ON code from inputs j 36 to register 7, while (since input 31 and it was not necessary to access the trigger 15) the ON code on the Vits at output 9, i.e. the next command MP will execute th already in the cube ON. Return to the original cube occurs in a similar way.

The second mode is implemented when the fourth and fifth transition commands appear at the input 4 (see Table 1). 15

The fast transfer process is shown on the example of a fragment of the transfer program from the cube 00 to the OM cube (see Table 3).

  20

In order to perform a quick data transfer, it is necessary to determine the kil in which it will be sent — for this purpose, the code of the LM cube 25 is formed in A for the main program (for example, using the KV1 command) and written to the OUT command in register 8 with address L, at the same time, in the second cycle of the transition command (M4), the MOV is formed 1 at the output 34 of the second element And 16, which opens the third register 8 for the time M4, thereby setting a temporary super-address.

The process is as follows. With the appearance of one of the commands 35 MOV M, A, or go MOV A, M, at output 27 of the second element OR 14, 1 appears. on the falling edge of which the trigger 15 is set to 1, which is fed to the second 33 input of the second element 40, the first input of which receives the signal M1, and opening 34 is formed at the output 34, which arrives at the register release control input 8. Reset trigger 15 is realized by the output signal of the one-shot 18, which is triggered by the falling edge of the signal 34.

Claims (1)

Claims 50 A memory addressing device containing an address decoder, a jump instruction decoder, two registers, a trigger, a delay element, two AND elements and an OR element, and the device's address- output is connected to the input of the device's lower-order bits and the address decoder, the first output of which is connected to the sync input of the first register, the information input, the installation input to O and the output of which is connected respectively to the information input of the device, the reset input of the device to the information input of the second register, synchronization input and the installation input in About which is connected respectively;: to the OUTPUT of the first elmvnt and and to the reset input of the device, the information input of which is connected to the input of the transition command decoder, the first group of outputs that is connected to the inputs of the first element OR whose output is connected to the counting input of the first trigger, whose output through the delay element is connected to the first input of the first element I, the second input and output of which are connected respectively to the input of the sign of transition to another cube of the device memory and to the installation input and in O of the first trigger, which is the fact that, in order to improve speed, a second OR element, two NOT elements, a second trigger, a one-shot, third register, and the input of the transfer to another device memory cube is connected to the sample input of the transfer instruction decoder and through the first element NOT to the first input of the second element AND, the second input and output of which are connected respectively to the output of the second trigger and to the input of the third register sample, information input, installation input Oh and sync that Connected respectively to the information input of the device, the reset input of the device and the second output of the address decoder, the gate input of the address decoder is connected to the input of the sign of the presence of the higher address bits of the device, the input of the signs of writing and reading are the outputs of the signs respectively write and read the device, the second group outputs of the decoder of the transition commands is connected to the inputs of the second element OR, the output of which is connected to the counting input of the second trigger, the input of the installation of which is connected to the output of the bottom of the vibrator, the output of the second element And connected to the input of the one-shot, through the second element NOT - to the input of the sample of the second register, the output of which is combined with the output of the third register and 00 00 00 N XX40 XX42 XX44 ADDR MVI A, o Memory Cube Code ON stored in battery (A) OUT Z Content A is written to register 6 with address Z CALL ADDR Transition to Cube ON with ADDR addresses Program execution Hereinafter addresses are given conditionally. connected to the high-order output of the device address. Table 1 Table 3