SU1718399A2 - Redundant system - Google Patents

Abstract

The invention relates to automation and computing, can be used in the design of computing systems and devices with increased reliability. The aim of the invention is to enhance the functionality of the system by providing a channel-to-channel mode. The system contains a restoring authority 2, and in each reservation channel there is a redundant computing device 1, a monitoring and control unit 3, a decoder 8, a register 9. a multiplexer 10, an AND 16 element and an OR 17 element.

Description

The invention relates to automation and computer technology, can be used in the design of computer systems and devices of high reliability.

Redundant system for auto Ns 1584137 contains a reducing organ. and in each reservation channel, a redundant computing device, wherein the information output of the computing device of each channel is connected to the corresponding information input of the reducing organ, the output of which is connected to the information input of the computing device, each backup channel also contains a control and control unit, a decoder, a register and a multiplexer, decoder inputs in each backup channel. information inputs of the register and address inputs of the multiplexer are connected to the corresponding outputs of the recovering organ, the outputs of the register are connected to the information inputs of the multiplexer, the output of which is connected to the corresponding control input of the recovering organ, in each backup channel the register gating input is connected to the first output of the decoder, the information output of the redundant computing the device is connected to the first input of the control and management unit, to the second input of which is connected n is the output of the restoring authority, in each backup channel the interrupt inputs of the redundant computing devices are connected to the interrupt output of the control and control unit, the information output of the control and control unit of each redundant channel is connected to the correction inputs of the control and control units of the remaining redundant channels.

The restoring organ is multi-bit in terms of bit depth of information inputs, in each category, the restoring organ contains a majority element and the number of redundancy channels with unequal elements, moreover, the information inputs of the restoring organ are connected to the inputs of the majority element and the first input of the corresponding unequal element, and the control inputs are connected to the second inputs of the corresponding disambiguation elements, the outputs of which are connected to the inputs of the majority element, Exit which is the output of the corresponding reducing body discharge.

A disadvantage of the known system is the limitation of its functionality due to the complexity of implementing the exchange of information of a three-channel structure with single-channel (non-reserved) devices.

The need for organizing such an exchange arises in almost all highly reliable redundant monitoring and control systems 10 in the process of debugging software, tuning, preparatory and routine maintenance. In such operations, non-redundant 15 devices for documenting and displaying information, tools for debugging programs, etc. can be connected to a three-channel system. The provision of this mode in systems with majority redundancy requires the input of information from 20 single-channel devices into three channels, which causes large additional hardware costs for switching the corresponding signals.

In the well-known system, access to I / O devices is organized on the main principle (at the address). In this case, the input of ot data from one unreserved device into three channels requires a significant increase in equipment, which may be unacceptable. For an example, if the addressing to input-output devices is via an η-bit bus, then the number of information inputs of the multiplexer that controls the operating mode of the recovering 35 organ increases by 2 bits (for 8 bits of the address, there are 256 inputs of the multiplexer). The implementation of such a scheme on standard microcircuits is possible only with their cascade connection, which significantly increases the amount of equipment 40 and reduces performance.

The purpose of the invention is the expansion of the functionality of the system by providing a channel-by-channel exchange mode. 45 The goal is achieved by the fact that in a redundant system containing a restoring body, and in each backup channel redundant computing device. 50, the information output of the computing device of each channel is connected to the corresponding information input of the reducing organ, the output of which is connected to the information input of the computing device, which also contains a control and control unit, a decoder, a register, and a multiplexer, and the decoder inputs in each redundancy channel. the information inputs of the register and the address inputs of the multiplexer are connected to the corresponding outputs of the recovering organ, the outputs of the register are connected to the information inputs of the multiplexer, the output of which is connected to the corresponding control input of the recovering organ, in each backup channel the register gating input is connected to the first output of the decoder. the information output of the redundant computing device is connected to the first input of the monitoring and control unit, the output of the restoring organ is connected to the second input of each redundancy channel, the interrupt inputs of the redundant computing devices are connected to the interrupt output of the monitoring and control unit, the information output of the monitoring and control unit of each redundant the channel is connected to the correction inputs of the control and management units of the remaining reserved channels, is not multi-bit in terms of bit depth of information inputs, in each category, the reducing body contains a majority element and the number of redundancy channels with unequal elements, moreover, the information inputs of the reducing body are connected to the inputs of the majority element and the first inputs of the corresponding disambiguation element, and the control inputs are connected to the second inputs of the corresponding disambiguity elements the outputs of which are connected to the inputs of the majority element, the output of which is the output ohm of the corresponding discharge of the restoring organ, the AND and OR elements are introduced into each reservation channel, the output of the OR element is connected to the first input of the AND element, the second input of which is connected to the corresponding output of the restoring organ, and the output to the gating input of the multiplexer, the first input of the OR element of the first channel is connected to the second input of the OR element of the second channel and the output of the blocking of the third channel. the second input of the OR element of the first channel is connected to the first input of the OR element of the third channel and the blocking output of the second channel, the first input of the OR element of the second channel is connected to the second input of the OR element of the third channel and the blocking output of the first channel.

In FIG. 1 shows a functional diagram of a redundant system: in FIG. 2 option to connect the information inputs of the multiplexer to the output of the register; in FIG. 3 is an embodiment of a control and management unit; in FIG. 4 is a diagram of a microprocessor module; in FIG. 5 is a diagram of an input / output module; FIG. 6 is a diagram of a regenerating organ.

The system contains (Fig. 1) redundant computing devices 1. restoring organ 2, control and control units 3, interrupt outputs 4, microprocessor module 5, memory module 6.

I / O module 7, decoder 8. Register 9 (backup section numbers), multiplexer 10. input bus 11, output bus 12, interrupt input 13, bi-directional bus 14 of device 1, outputs 15 of decoders, element 14 16, OR element 17, and output 18 lock.

Haha. 2, inverters 19 and 21 and a decoder 20 are indicated.

The control and management unit 3 (FIG. 3) consists of inverters 22-49, elements of unequality 5077, 8-input elements AND-NOT 78-81, elements OR 82 and AND 83, trigger 84, element 85 with an open collector, shaper 86, inverter

87, decoder 88 and register 89,

Microprocessor module 5 (Fig. 4) contains inverters 90 and 91, microprocessor 92. Elements And 93-97, bus driver 98 and register 99.

The input-output module 7 (Fig. 5) consists of bus drivers 100, 101 and 103, a decoder 102, inverters 104, 105 and 107 and a parallel programmable interface 106.

In FIG. 6 shows a reducing organ 2 by one discharge, made on the elements of unequality 108 and 110 and the majority elements 111.

The system operates as follows.

In devices 1, three microprocessor modules 5 operate synchronously according to the same programs stored in memory modules 6. The information exchange between devices 1 and peripheral is carried out via I / O modules 7 via bi-directional buses 14. Output buses 12, intended for transmitting addresses, data, and control signals, are a set of communication lines coming from microprocessor modules 5 through a reducing organ 2 and input buses 11 to memory modules 6 and I / O 7, and vice versa, from memory modules 6 and I / O 7 to microprocessor modules 5.

The system continues to function correctly if any of the redundant components fails;

If a failure of a particular module or backup section is detected, the system has the ability to switch

Ί the installer to the operating mode from one of the two remaining serviceable modules of this type.

The restoring organ performs the majority function of choosing two out of three over the input signals. By control signals, it transmits information from one of two serviceable channels to its output.

In the initial mode, the registers 9 (Fig. 1 and 2) are set to zero. During operation of the system, in the absence of writing to the registers 9, zero signals are also present at the outputs of the multiplexers 10. The restoring organ 2 in this case performs a majority function.

Switching the regenerating body to the operation mode from one working channel is carried out by applying to the corresponding inputs single control signals from multiplexers 10. If a failure is detected in the first channel, then single signals must be supplied from the multiplexers of the first and second (or third) channels. in case of failure in the second channel - from the multiplexers of the second and third (or first) channels, in the third channel - from the first and third (or second) channels.

When a failure is detected, information corresponding to the number of the failed reservation section is recorded in the registers 9. If it is necessary to disable the failed section, for example, in the first channel, then the channels are recorded in the registers of the outputs of the multiplexers of which single control signals must be supplied to switch the regenerating organ.

’Selective recording in the registers 9 from the general output of the restoring body 2 is carried out by the corresponding connection of the outputs of the decoders 8 to the control inputs of the registers. In FIG. 2 shows the connection of the output 1 of the decoder 20 to the control input of the register 9 for the first channel. For the second channel, the output • of decoder 20 should be connected to the • control input of register 9. For the third channel, output 3.

The development of control signals for switching the regenerating body is as follows.

If it is necessary to disconnect a faulty microprocessor module in the category Q4 of register 9 of the corresponding channels, a logical unit is written. When the microprocessor module 5 is subsequently accessed by buses using the Write or Output commands, the signals of a logical unit are formed at the outputs of the multiplexers 10 of the corresponding channels, which disconnects the data buses (addresses) for the duration of the indicated access.

At the command “Input”, the multiplexer 10 switches the signal from the discharge Q3 to its output. If a logical unit is written in this category, then the data buses are disconnected from the corresponding I / O module,

By the Read command, the output state of the multiplexer 10 is determined by the signals at the address input of AO and the information inputs DO, D1. Signals Input, Output, Record with this command are absent. By writing the necessary information to the bits Q0, Q1 of register 9, it is possible to disable the memory area at address A15.

The generation of single output signals from the corresponding multiplexers 10 when working with non-redundant input-output devices is carried out by applying a logic unit signal (since the outputs of the multiplexers are inverse) to the gating input (page) of the multiplexer 10.

If an unreserved input-output device is installed in the first channel, then when accessing it at the appropriate address, the input-output module 7 of the first channel generates a single signal coming through the blocking output 18, the OR elements 17 of the second and third channels to the corresponding inputs of the And 16 elements, According to the control signal, Input at the input of p ”of multiplexers 10 from the outputs of the elements And 16 of the second and third channels, single signals appear for switching the restoring organ 2. Similarly for non-reserved devices IO installed in the other channels are formed by the signals from the respective locking unit 18 outputs levels at the outputs of multiplexers 10.

The definition of a failed reservation site is as follows,

In blocks 3 control and management (Fig.

3) in the absence of malfunctions, the trigger 84 is set to the initial state, and on the elements 22-83, bitwise comparison of the information at the output of the restoring organ 2 with the information on the buses 12 is carried out. The signal mismatch is stored on the trigger 84, the output signal of which through the inverters 85 goes to the inputs of the shapers 86, generating a write pulse to the registers 89. Thus, the registers 89 store information that characterizes the number of the failed channel and the state of the majority buses, for example, control signals (3 pis, Reading, Input, Output), data (DO-D7). address (AO-A15), a sign of an inconsistency in the data buses (from element 81).

The signal from the combined outputs of the Elements NOT 85 also arrives at the interrupt inputs of microprocessor modules

5. Having received this signal, the computing device polls the register 89 through the restoring authority 2 and processes the received information. The capacity of the registers 89 depends on the required depth of diagnosis of the malfunction. In FIG. 3, register 89 is shown at 8 digits. The purpose of the control signals arriving at the inputs of the registers is as follows: Record - record data D0-D7 at address A0-A15 from microprocessor modules to memory modules: Input - enter data from input-output modules to microprocessor modules; Output - data output from microprocessor modules to input-output modules. Writing in bits D0-D2 of the register code 001 25 corresponds to the failure of the third channel, 100 of the first channel, 010 - of the second channel. By bits D3-D6, the type of the failed module is determined, for example, the code 1000 corresponds to the failure of the memory module. 1 - indicates a 30 mismatch in the data buses, and 000 ^{J indicates} the presence of a Read ”memory signal. By discharge D7, the number of the faulty memory drive is determined. With increasing bit depth of the register 89, the depth of diagnosis also increases.

The microprocessor 92 (Fig. 4) has a bi-directional data line D0-D.7, which is converted into a unidirectional signal by a Receive signal. Register 99 is designed to store a state that determines the type of instruction executed by the Microprocessor 92. The state is recorded by the signal from the And 93 element. By the state of the register 99 and the signals from the microprocessor 92, the Write, Read control signals are formed on the And 94-97 elements. Input and Output ”.

The main element of the input-output module (Fig. 5) is a programmable parallel interface 106 with three ports A, B, C at addresses A0-A1.

Non-redundant I / O devices can be connected to the corresponding address, data, and control buses in each channel through bus drivers 100, 101, and 103 and elements 104 and 105. The decoder 102 generates selection signals for elements 106 operating in three channels synchronously with redundant I / O devices through bus 14 and blocking signals (output 18) when computing devices 1 are accessed at addresses corresponding to non-reserved input-output devices.

If non-redundant I / O devices are installed on each channel, then their addresses must be different. When outputting, the data arrives in three channels at the same time, but only the device with the corresponding address responds to this data. When you enter the formation of a single signal at the output 18 provides the corresponding switching of the regenerating body 2.

Element 111 (Fig. 6) performs the majority function of selecting four out of six over the output signals. The ambiguity elements 108110 invert the input information when they arrive at the control inputs of the reducing organ of logical units or repeat the information at zero signals at the control inputs.

Claims (1)

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