JPS5745727A - Dissidence circuit - Google Patents
Dissidence circuitInfo
- Publication number
- JPS5745727A JPS5745727A JP12060980A JP12060980A JPS5745727A JP S5745727 A JPS5745727 A JP S5745727A JP 12060980 A JP12060980 A JP 12060980A JP 12060980 A JP12060980 A JP 12060980A JP S5745727 A JPS5745727 A JP S5745727A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- level
- circuit
- circuits
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000295 complement effect Effects 0.000 abstract 3
- 230000010355 oscillation Effects 0.000 abstract 3
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
Landscapes
- Logic Circuits (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Abstract
PURPOSE:To detect the dissidence of a complementary input signal surely, by controlling an oscillating circuit through the output of two rectifying circuits in which the discharge time is set longer than the period of an input signal and complementary input signals with a prescribed period are rectified. CONSTITUTION:Complementary input signals (a), (b) are respectively inputted to input terminals A, B, then a rectifying circuit 1 is charged at level 1 of the signal (a) and a rectifying circuit 2 is charged when the signal (b) is at level 1. Since the discharge time of the circuits 1, 2 is set slightly longer than the period of the signal (a) and (b), when the signals (a), (b) are repetitively inputted in a prescribed period, the rectified output of the circuits 1, 2 keeps the level 1. Thus, oscillating circuits 3, 4 always output the oscillating output in a prescribed frequency and supply it to an oscillation circuit 5. Thus, the oscillation circuit 5 also outputs the oscillation signal in a prescribed frequency, and this is rectified to output a dissidence signal c of level 1. If the signals (a), (b) are coincided at a timing, the signal of level 1 is outputted only to one of the circuits 1, 2, and the dissidence signal C of level 1 from the circuit 5 is stopped.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12060980A JPS5745727A (en) | 1980-09-02 | 1980-09-02 | Dissidence circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12060980A JPS5745727A (en) | 1980-09-02 | 1980-09-02 | Dissidence circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5745727A true JPS5745727A (en) | 1982-03-15 |
JPS6118374B2 JPS6118374B2 (en) | 1986-05-12 |
Family
ID=14790475
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12060980A Granted JPS5745727A (en) | 1980-09-02 | 1980-09-02 | Dissidence circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5745727A (en) |
-
1980
- 1980-09-02 JP JP12060980A patent/JPS5745727A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6118374B2 (en) | 1986-05-12 |
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