JPS54113236A - Logical signal transfer circuit - Google Patents
Logical signal transfer circuitInfo
- Publication number
- JPS54113236A JPS54113236A JP1981078A JP1981078A JPS54113236A JP S54113236 A JPS54113236 A JP S54113236A JP 1981078 A JP1981078 A JP 1981078A JP 1981078 A JP1981078 A JP 1981078A JP S54113236 A JPS54113236 A JP S54113236A
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- level
- turned
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
PURPOSE:To prevent pulsative noise from being generated in the transfer output, by providing a transmission gates, which set forcedly one logical level, in the output of a transfer control transmission gate and controlling them with a fixed time difference. CONSTITUTION:When transfer control signal RE is high-level, transfer control transmission gates MISFETQ2 and MISFETQ1 are turned on and off respectively, and gate circuit NOR is opened to transfer transmission signal 1A to output OUT. Next, since signal RE' becomes high-level first at the change time of signal RE to a low level, MISFETQ2 is turned off, and next, MISFETQ1 is turned on after, thereby holding forcedly the output terminal at low level -VDD. Pulsative noise is prevented from being generated in the output by this time difference.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1981078A JPS54113236A (en) | 1978-02-24 | 1978-02-24 | Logical signal transfer circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1981078A JPS54113236A (en) | 1978-02-24 | 1978-02-24 | Logical signal transfer circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54113236A true JPS54113236A (en) | 1979-09-04 |
Family
ID=12009679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1981078A Pending JPS54113236A (en) | 1978-02-24 | 1978-02-24 | Logical signal transfer circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54113236A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5943629A (en) * | 1982-09-02 | 1984-03-10 | Matsushita Electric Ind Co Ltd | Electronic switch device |
-
1978
- 1978-02-24 JP JP1981078A patent/JPS54113236A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5943629A (en) * | 1982-09-02 | 1984-03-10 | Matsushita Electric Ind Co Ltd | Electronic switch device |
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