JPS5748825A - Schmitt circuit - Google Patents
Schmitt circuitInfo
- Publication number
- JPS5748825A JPS5748825A JP12432980A JP12432980A JPS5748825A JP S5748825 A JPS5748825 A JP S5748825A JP 12432980 A JP12432980 A JP 12432980A JP 12432980 A JP12432980 A JP 12432980A JP S5748825 A JPS5748825 A JP S5748825A
- Authority
- JP
- Japan
- Prior art keywords
- fets
- driver
- channel
- circuit
- schmitt circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
Abstract
PURPOSE:To set the high or low level of threshold of a circuit independently, by constituting the circuit with three sets of inverters consisting of complementary IG-FETs and a driver consisting of cascade connection of the IG-FETs. CONSTITUTION:A Schmitt circuit is constituted with three sets of inverters 16-18 consisting of complementary IG-FETs 7, 8-11, 12, and a driver 19 consisting of the cascade connection of P channel IG-FETs 5, 13 and N channel IG-FETs 6, 14. The high level of the threshold TH of the Schmitt circuit is decided with the gm of the FETs 6, 14 of the driver 19 and of a P channel IG-FET9 of an inverter 17, and the low level is the ratio of gm between the FETs 5, 13 of the driver 19 and the N channel IG-FET10 of the inverter 17. The FET14 turns on only when the input level changes from 0 to 1 and the FET13 turns on only when the input level changes from 1 to 0, then the high level of the TH of the Schmitt circuit is obtained by adjusting the gm of the FET6 or 14 and the low level is obtained by adjusting the gm of the FET5 or 13 independently.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12432980A JPS5748825A (en) | 1980-09-08 | 1980-09-08 | Schmitt circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12432980A JPS5748825A (en) | 1980-09-08 | 1980-09-08 | Schmitt circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5748825A true JPS5748825A (en) | 1982-03-20 |
Family
ID=14882636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12432980A Pending JPS5748825A (en) | 1980-09-08 | 1980-09-08 | Schmitt circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5748825A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0230306A2 (en) * | 1986-01-22 | 1987-07-29 | Nec Corporation | Schmitt trigger circuit |
JPH05327461A (en) * | 1992-05-26 | 1993-12-10 | Mitsubishi Electric Corp | Input circuit |
-
1980
- 1980-09-08 JP JP12432980A patent/JPS5748825A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0230306A2 (en) * | 1986-01-22 | 1987-07-29 | Nec Corporation | Schmitt trigger circuit |
US4719367A (en) * | 1986-01-22 | 1988-01-12 | Nec Corportion | Schmitt trigger circuit |
JPH05327461A (en) * | 1992-05-26 | 1993-12-10 | Mitsubishi Electric Corp | Input circuit |
JP2905000B2 (en) * | 1992-05-26 | 1999-06-14 | 三菱電機株式会社 | Input circuit |
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