JPS57197927A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS57197927A
JPS57197927A JP56083500A JP8350081A JPS57197927A JP S57197927 A JPS57197927 A JP S57197927A JP 56083500 A JP56083500 A JP 56083500A JP 8350081 A JP8350081 A JP 8350081A JP S57197927 A JPS57197927 A JP S57197927A
Authority
JP
Japan
Prior art keywords
data
fets
level
input
turn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56083500A
Other languages
Japanese (ja)
Inventor
Hitoshi Matsuda
Akira Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56083500A priority Critical patent/JPS57197927A/en
Publication of JPS57197927A publication Critical patent/JPS57197927A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Abstract

PURPOSE:To decrease the number of input and output pins by providing an input circuit which generates two signals by a ternary level signal and an output circuit which converts the two signals into the ternary level signal. CONSTITUTION:A composite output driving circuit consists of N channel IGFETs (T1-T4). When data DA and DB have a high level, the FETs T2, T3 and T4 turn on and output data DC has low level. When the data DA has the high level and the DB has the low level, the FETs T2 and T3 turn on and the T4 turns off, so that the data DC has an intermediate level. When the data DA and DB have the low level, the FETs T2 and T4 turn off and the data DC has the high level. Further, the composite input receiving circuit composed of IGFETs (T5-T9) separates ternary input data by making the threshold voltages of the FETs T6 and T8 different.
JP56083500A 1981-05-30 1981-05-30 Semiconductor integrated circuit device Pending JPS57197927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56083500A JPS57197927A (en) 1981-05-30 1981-05-30 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56083500A JPS57197927A (en) 1981-05-30 1981-05-30 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS57197927A true JPS57197927A (en) 1982-12-04

Family

ID=13804191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56083500A Pending JPS57197927A (en) 1981-05-30 1981-05-30 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57197927A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170935A (en) * 1983-03-17 1984-09-27 Matsushita Electric Ind Co Ltd Transmitting device of signal

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50102235A (en) * 1974-01-09 1975-08-13
JPS5299031A (en) * 1976-02-16 1977-08-19 Hitachi Ltd Three value input detecting circuit
JPS53128240A (en) * 1977-04-13 1978-11-09 Philips Nv Integrated circuit
JPS5492034A (en) * 1977-12-29 1979-07-20 Matsushita Electric Ind Co Ltd Integrated circuit
JPS54110774A (en) * 1978-02-17 1979-08-30 Mitsubishi Electric Corp Logic circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50102235A (en) * 1974-01-09 1975-08-13
JPS5299031A (en) * 1976-02-16 1977-08-19 Hitachi Ltd Three value input detecting circuit
JPS53128240A (en) * 1977-04-13 1978-11-09 Philips Nv Integrated circuit
JPS5492034A (en) * 1977-12-29 1979-07-20 Matsushita Electric Ind Co Ltd Integrated circuit
JPS54110774A (en) * 1978-02-17 1979-08-30 Mitsubishi Electric Corp Logic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170935A (en) * 1983-03-17 1984-09-27 Matsushita Electric Ind Co Ltd Transmitting device of signal

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