JPS54110774A - Logic circuit - Google Patents
Logic circuitInfo
- Publication number
- JPS54110774A JPS54110774A JP1781878A JP1781878A JPS54110774A JP S54110774 A JPS54110774 A JP S54110774A JP 1781878 A JP1781878 A JP 1781878A JP 1781878 A JP1781878 A JP 1781878A JP S54110774 A JPS54110774 A JP S54110774A
- Authority
- JP
- Japan
- Prior art keywords
- vin
- circuit
- vth
- output
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0002—Multistate logic
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To decrease the number of terminals of the package by giving the potential change of more than three points to one unit of the external input terminal to secure the logic and thus to deliver three kinds of the truth value and thus saving one external input terminal. CONSTITUTION:When input voltage Vin's absolute value ¦Vin¦ is more than VSS and at the same time less than threshold voltage (¦VTH¦), enhancement FETQ1 does not conduct. Ant the output of inverter circuit 1 features the L-potential under VO VSS, and both V3 and V4 feature the L-potential since Vin is supplied to the input of NOR circuit 2 and 3. When Vin is under the 2nd state, Q1 conducts. And ¦VO¦<¦VTH¦ is secured owing to the relation of the conductance of Q1 as gm2 of gm1>>Q2, and thus circuit 1 does not conduct yet with the output of L and V3 of H respectively. With Vin under the 3rd state, ¦VO¦>¦VTH¦ is satisfied with the output of L for circuit 1 and V3 of L each. And V4 features H. In such way, the three kinds of the truth value can be delivered through one unit of the external input terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1781878A JPS54110774A (en) | 1978-02-17 | 1978-02-17 | Logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1781878A JPS54110774A (en) | 1978-02-17 | 1978-02-17 | Logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54110774A true JPS54110774A (en) | 1979-08-30 |
Family
ID=11954304
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1781878A Pending JPS54110774A (en) | 1978-02-17 | 1978-02-17 | Logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54110774A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57197927A (en) * | 1981-05-30 | 1982-12-04 | Toshiba Corp | Semiconductor integrated circuit device |
-
1978
- 1978-02-17 JP JP1781878A patent/JPS54110774A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57197927A (en) * | 1981-05-30 | 1982-12-04 | Toshiba Corp | Semiconductor integrated circuit device |
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