JPS553234A - Self-supporting cmos latch circuit - Google Patents

Self-supporting cmos latch circuit

Info

Publication number
JPS553234A
JPS553234A JP7559378A JP7559378A JPS553234A JP S553234 A JPS553234 A JP S553234A JP 7559378 A JP7559378 A JP 7559378A JP 7559378 A JP7559378 A JP 7559378A JP S553234 A JPS553234 A JP S553234A
Authority
JP
Japan
Prior art keywords
terminal
turned
transistor
level
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7559378A
Other languages
Japanese (ja)
Inventor
Mitsuo Isobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7559378A priority Critical patent/JPS553234A/en
Publication of JPS553234A publication Critical patent/JPS553234A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors

Abstract

PURPOSE:To secure absorption of the level fluctuation caused by the noise under the latch state as well as to reduce the power consumption by using one unit of the timing signal input terminal as the external control terminal and thus lessening the load of the terminal. CONSTITUTION:CMOS inverter 2 consists of transistor Q3 and Q4 which are similar to n-channel MOS transistor Q1 and p-channel MOS transistor Q2 which form C-MOS inverter 1. When the ''H'' level is applied to input A with application of ''H'' level to timing input terminal E, transfer gate 13 is turned on with points B, C, L and D turned to ''H'' respectively. For transfer gate 24 at that instant, points B and D feature the identical potential to each other since transistor Q11 is off with Q12 on each, and the identical potential is held even if terminal E is turned to ''L''. In the same way, the ''L'' is kept at point B and D even in the case of the input at ''L''. Thus, the noise if caused in the latch state can be absorbed to point D since Q11 or Q12 is on.
JP7559378A 1978-06-22 1978-06-22 Self-supporting cmos latch circuit Pending JPS553234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7559378A JPS553234A (en) 1978-06-22 1978-06-22 Self-supporting cmos latch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7559378A JPS553234A (en) 1978-06-22 1978-06-22 Self-supporting cmos latch circuit

Publications (1)

Publication Number Publication Date
JPS553234A true JPS553234A (en) 1980-01-11

Family

ID=13580644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7559378A Pending JPS553234A (en) 1978-06-22 1978-06-22 Self-supporting cmos latch circuit

Country Status (1)

Country Link
JP (1) JPS553234A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57201321A (en) * 1981-06-03 1982-12-09 Nec Corp Latch circuit
JPS5861538U (en) * 1981-10-21 1983-04-25 日本電気株式会社 latch circuit
JPS58103222A (en) * 1981-12-15 1983-06-20 Nec Corp Flip-flop circuit
JPS5936418A (en) * 1982-08-24 1984-02-28 Nec Corp Latch circuit
JPS59200520A (en) * 1983-04-27 1984-11-13 Hitachi Ltd Cmos flip-flop circuit
FR2578125A1 (en) * 1985-02-28 1986-08-29 Efcis STATIC BISTABLE ROCKET IN CMOS TECHNOLOGY
JPS6220411A (en) * 1985-07-17 1987-01-29 クセルト　セントロ・ステユデイ・エ・ラボラトリ・テレコミニカチオ−ニ・エツセ・ピ−・ア− Sequential logical base element for cmos technology operating by one clock signal
JPH02196517A (en) * 1989-01-25 1990-08-03 Nec Corp Data transmission circuit

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57201321A (en) * 1981-06-03 1982-12-09 Nec Corp Latch circuit
JPS5861538U (en) * 1981-10-21 1983-04-25 日本電気株式会社 latch circuit
JPS58103222A (en) * 1981-12-15 1983-06-20 Nec Corp Flip-flop circuit
JPH0157848B2 (en) * 1981-12-15 1989-12-07 Nippon Electric Co
JPS5936418A (en) * 1982-08-24 1984-02-28 Nec Corp Latch circuit
JPS59200520A (en) * 1983-04-27 1984-11-13 Hitachi Ltd Cmos flip-flop circuit
FR2578125A1 (en) * 1985-02-28 1986-08-29 Efcis STATIC BISTABLE ROCKET IN CMOS TECHNOLOGY
US4703200A (en) * 1985-02-28 1987-10-27 Societe pour l'Etude de la Fabrication des Circuits Integres Speciaux - E.F.C.I.S. Static bistable flip-flop circuit obtained by utilizing CMOS technology
JPS6220411A (en) * 1985-07-17 1987-01-29 クセルト　セントロ・ステユデイ・エ・ラボラトリ・テレコミニカチオ−ニ・エツセ・ピ−・ア− Sequential logical base element for cmos technology operating by one clock signal
JPH02196517A (en) * 1989-01-25 1990-08-03 Nec Corp Data transmission circuit

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