JPS59200520A - Cmos flip-flop circuit - Google Patents

Abstract

PURPOSE:To decrease the number of elements by providing a transmit gate consisting of a (p) or (n) channel MOSFET and a latch circuit which performs level compensation. CONSTITUTION:The (p) channel MOSFETQ1 forms the transmit gate which inputs an input signal D to a master latch circuit ML. Similarly, an (n) channel MOSFETQ4 forms a transmit gate which inputs the output signal of the latch circuit ML to a slave latch circuit SL. A clock signal C is applied to the gates of both FETs Q1 and Q4 in common. Each latch circuit ML (SL) consists of an output CMOS inverter IV1 (IV3) and a feedback COMS inverter IV2 (IV4) for level compensation. Thus, the number of elements is decreased.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a CMO3 (complementary MO3) flip-flop circuit composed of MOSFETs (insulated gate field effect transistors).
The present invention relates to a technique effective for a CMO3 integrated circuit device having n-way MOS flip-flops.

[Background technology]

As a CMOS flip-flop circuit, a master-slave CMOS flip-flop circuit as shown in FIG. 1 is well known. This flip-flop circuit consists of p-channel MO3FETQI, Q3 and n-channel MO3FET
Q2. CMO configured by connecting Q4 in parallel with each other.
3 transmission gates TI, T2 and CMOS inverter IVI
, the master latch circuit ML and CMO composed of IV2.
S inverter IV3. It consists of a slave latch circuit SL made up of IV4 and an inverter IV5 for forming an inverted clock signal C to be supplied to the transmission gates TI and T2. When the clock signal C is low level (OV), this flip-flop circuit has a transmission gate T
MO3FETQ1. Q2 is turned on, and the input signal is taken into the master latch circuit ML.

When the clock signal C is at a high level (Voo), MO3FETQ3, Q which constitutes the transmission gate T2
4 is turned on, and the output of the master launch circuit ML is taken into the slave latch circuit SL.

In the above CMOS flip-flop circuit, the above CMOS
By using the MO3 transmission gate, the correct signal level to be transmitted can be obtained on the output side. That is,
n-channel MOS FET or p-channel MO3
This is because if a transmission gate is constructed only from FETs, a level loss occurs at a high level or a low level only at the threshold voltage, and the signal level cannot be transmitted correctly. For this reason, the CMOS flip-flop circuit as shown in FIG. 1 has the disadvantage that the number of elements is relatively large.

[Purpose of the invention]

An object of the present invention is to provide a CMOS flip-flop circuit with a reduced number of elements.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an input signal passed through a transmission gate composed of an n-channel MO3FET or a p-channel MOSFET is input to a latch circuit composed of two CMOS inverters, and the feedback CMO of this launch circuit is
The S inverter performs level compensation.

[Embodiment 1] FIG. 2 shows a circuit diagram of an embodiment of the present invention. Each of the circuit elements shown in the figure is formed on a semiconductor substrate, such as silicon, by known CM O8 fabrication techniques.

Although not particularly limited, this embodiment shows a master-slave type flip-flop circuit.

That is, the p-channel MO3FET QI constitutes a transmission gate that takes in an input signal to the master latch circuit ML. Similarly, n-channel MO3FETQ4
This constitutes a transmission gate that takes in the output signal from the master latch circuit ML to the slave latch circuit SL. A clock signal C is commonly applied to the gates of both MO3FETs QI and Q4.

Each latch circuit ML (SL) described above has an output CMOS inverter IVI (IV
3) and a feedback CMOS inverter IV2 (IV4). These latch circuits ML and SL are
Transmission gate T1. In order to operate according to the signal level through T2, the feedback inverter IV2. I
The output impedance of each of V4 is set to a relatively large value within a range in which a level compensation operation, which will be described later, can be performed. Therefore, each of the latch circuits ML and SL has a logic threshold voltage that is approximately 1/2 of the source voltage VDD, and outputs an inverted signal according to the input signal level from the output terminal.

Next, the operation of this embodiment circuit will be explained.

If the clock signal C is now at a low level (ground potential of the circuit), the p-channel MOS FETQ 1 is turned on and transmits the input signal to the input of the master latch circuit ML. At this time, even if the input signal is at a low level (circuit ground potential OV), it will rise by the threshold voltage vth of the MO3FET QI. However, since the level is lower than the logic threshold voltage of the latch circuit ML, the output level of the inverter IVI becomes a high level (source voltage V DD ),
A level compensation operation is performed in which the output of the feedback inverter IV2 becomes low level and the potential of the input terminal is lowered to the ground potential. Note that if the input signal is at a high level, the p-channel MO3FETQ 1 transmits that level as is to the input of the master latch circuit ML. In this way, the master latch circuit ML incorporates the input signal into the low level period of the clock signal C while performing level compensation.

Next, when the clock signal C becomes high level (power supply voltage), the n-channel MO3FET Q4 is turned on and transmits the output signal of the master latch circuit ML to the input of the slave latch circuit SL.

At this time, even if the output signal of the master launch circuit ML is at a high level (power supply voltage V DD ), the MO3FE
The signal level (VDD-Vth) is lowered by the threshold voltage vth of TQ4. However, since the level is higher than the logic threshold voltage of the latch circuit SL, the output level of the inverter IV3 becomes a low level, and the output of the feedback inverter IV4 becomes a high level, reducing its input potential to the power supply voltage VDD. It performs a level compensation operation of raising the level. In addition,
When the output signal from the master latch circuit ML is at a low level, the n-channel MO3FET Q6 transmits that level as it is to the input of the slave latch circuit SL. In this way, the slave latch circuit SL is
While performing the level compensation, the master latch circuit M
The L output signal is taken in during the high level period of the clock signal C.

In this way, each latch circuit ML, SL compensates the level of its input signal, so that the inverter IVI
, IV3, etc., it is possible to prevent a relatively large direct current from flowing due to the input level being at an intermediate level, so that the low power consumption operation can be maintained.

This master-slave type flip-flop circuit operates by shifting the clock signal C by half a cycle and outputting the input signal through the master flip-flop and slave flip-flop.

(Embodiment 2) FIG. 3 shows a circuit diagram of another embodiment of the present invention.

In this embodiment, the MOS forming the transmission gate T1 is
The second point is that the FET is composed of an n-channel MO3FETQ2, and the MOSFET that constitutes the transmission gate 1-72 is composed of a p-channel MO3FETQ3.
This is different from the embodiment shown in the figure. Therefore, in this embodiment, the input signal is input to the master latch circuit ML during the high level period of the clock signal C, and the output of the master latch circuit ML is sent to the slave latch circuit SL during the low level period of the clock signal C. Signal acquisition is performed.

[Embodiment 3] FIG. 4 shows a circuit diagram of still another embodiment of the present invention.

In this embodiment, the transmission gates TI and T2 are constituted by, for example, n-channel MO3FETs Q2 and Q4 of the same conductivity type. Therefore, two-phase clock signals C1 and C2 are respectively applied to the gates thereof.

〔effect〕

(11 In this embodiment, the number of elements for configuring the master-slave type flip-flop circuit is a transmission gate of one conductivity type compared to the master-slave type flip-flop circuit shown in FIG. 1) MOSFET and an inverted clock Since an inverter for forming a signal is not required, an effect can be obtained in that a total of four MOSFETs can be reduced.

(2) As the number of elements is reduced, the number of wiring lines can also be reduced.

(3) Due to the above (11 and (2)), it is possible to achieve a high degree of integration in a semiconductor integrated circuit device including a large number of flip-flop circuits.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, a flip-flop circuit has one transmission gate MO3FET and one CM which receives the signal through this transmission gate MO5FET.
It may also be configured with an OS launch circuit.

In addition, a gate function is provided between the input clock terminal and the transmission gate MO3FET, a gate function is provided between the output of the slave latch circuit and the output terminal, or an additional circuit such as a cent input function or a reset input function is provided. It may be provided.

[Application field]

This invention can be widely used as a CMOS flip-flop circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of what can be considered as a CMOS flip-flop circuit, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. FIG. 4 is a circuit diagram showing still another embodiment of the present invention. Summer VI ~IV4--CMOS inverter, ML1...master latch circuit, SL...slave latch circuit 2

Claims (1)

[Claims] 1. n-channel MO3FET or p-channel MO3
1. A CMOS flip-flop circuit comprising a transmission gate composed of a FET, an output CMOS inverter that receives an input signal through the transmission gate, and a latch circuit composed of a feedback CMOS inverter. 2. The flip-flop circuit is configured such that two flip-flop circuits are connected in series, and the master-slave operation is performed by operating the transmission gates in time series. CMOS flip-flop circuit. 3. The transmission gate of the flip-flop circuit in the previous stage and t
& stage transmission gates are MOSFETs of opposite conductivity type.
3. The flip-flop circuit according to claim 2, wherein the flip-flop circuit is constructed by: