JPS56122229A - Level converting circuit - Google Patents

Level converting circuit

Info

Publication number
JPS56122229A
JPS56122229A JP2510280A JP2510280A JPS56122229A JP S56122229 A JPS56122229 A JP S56122229A JP 2510280 A JP2510280 A JP 2510280A JP 2510280 A JP2510280 A JP 2510280A JP S56122229 A JPS56122229 A JP S56122229A
Authority
JP
Japan
Prior art keywords
level
signal phi
vdd
impedance
converting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2510280A
Other languages
Japanese (ja)
Inventor
Tetsuya Iida
Kenro Sakagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2510280A priority Critical patent/JPS56122229A/en
Publication of JPS56122229A publication Critical patent/JPS56122229A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the power consumption amount, by using the 1st and 2nd impedance means plus the 3rd impedance means that has no overlap between its period of a low impedance state and the 1st impedance means. CONSTITUTION:When the clock signal phi is at the L level, the output signal phi' of the inverter consisting of the transistors Q14 and Q15 is set at the H level, i.e., the Vdd volts. In this instant, the transistor Q13 is turned off, the level of the signal phi' is set at the value that is obtained by dividing the Vdd in accordance with the impedance ratio between the transistors Q11 and Q12. On the other hand, the signal phi' is set at the L level, i.e., 0 volt when the clock signal is at the H level. In this instant, the Vdd is applied to the gate of the transistor Q13. As a result Q13 is turned on and the signal phi' is set at the L level, i.e., 0 volt.
JP2510280A 1980-02-29 1980-02-29 Level converting circuit Pending JPS56122229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2510280A JPS56122229A (en) 1980-02-29 1980-02-29 Level converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2510280A JPS56122229A (en) 1980-02-29 1980-02-29 Level converting circuit

Publications (1)

Publication Number Publication Date
JPS56122229A true JPS56122229A (en) 1981-09-25

Family

ID=12156553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2510280A Pending JPS56122229A (en) 1980-02-29 1980-02-29 Level converting circuit

Country Status (1)

Country Link
JP (1) JPS56122229A (en)

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