JPS5765927A - Logical operation circuit - Google Patents

Logical operation circuit

Info

Publication number
JPS5765927A
JPS5765927A JP14208680A JP14208680A JPS5765927A JP S5765927 A JPS5765927 A JP S5765927A JP 14208680 A JP14208680 A JP 14208680A JP 14208680 A JP14208680 A JP 14208680A JP S5765927 A JPS5765927 A JP S5765927A
Authority
JP
Japan
Prior art keywords
gate
output
prevent
constitution
inactive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14208680A
Other languages
Japanese (ja)
Inventor
Katsuhisa Tachikawa
Kazuharu Hirachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14208680A priority Critical patent/JPS5765927A/en
Publication of JPS5765927A publication Critical patent/JPS5765927A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type

Landscapes

  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To prevent the output from being a floating state, by providing an element, which is turned on under the inactive state, in the output stage in a ratio type NOR gate of a multistage constitution. CONSTITUTION:When a two-stage cascaded NOR gate is made, inactive, MOS transistors QL1 and QL2 are made nonconductive. At this time, the consumption current in both NOR gate parts is zero, and the potential of an output (point A) is fixed to VSS with a low impedance by an MOS transistor QR, which operates complementarily for the transistor QL2, to prevent a floating state. NOR gate inputs IN1-INn and A100-An1 are applied to driving MOS transistors QD1-QDn and QD100-QDn1 to make transistors QL1 and QL2 conductive, thus operating NOR.
JP14208680A 1980-10-13 1980-10-13 Logical operation circuit Pending JPS5765927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14208680A JPS5765927A (en) 1980-10-13 1980-10-13 Logical operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14208680A JPS5765927A (en) 1980-10-13 1980-10-13 Logical operation circuit

Publications (1)

Publication Number Publication Date
JPS5765927A true JPS5765927A (en) 1982-04-21

Family

ID=15307095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14208680A Pending JPS5765927A (en) 1980-10-13 1980-10-13 Logical operation circuit

Country Status (1)

Country Link
JP (1) JPS5765927A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186198A (en) * 1983-04-08 1984-10-22 Seiko Epson Corp Semiconductor storage device
JPS60165119A (en) * 1984-02-08 1985-08-28 Nec Corp Multi-input cmos logic circuit
JPS63141412A (en) * 1986-12-03 1988-06-13 Toshiba Corp Logic circuit
FR2768872A1 (en) * 1997-09-25 1999-03-26 Sgs Thomson Microelectronics OR-EXCLUSIVE LOGIC HOLDER WITH FOUR ADDITIONAL TWO TO TWO AND TWO ADDITIONAL OUTPUTS, AND FREQUENCY MULTIPLIER INCORPORATING IT
EP1277283B1 (en) * 2000-03-07 2004-09-08 Honeywell International Inc. High speed logic family

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5486242A (en) * 1977-12-21 1979-07-09 Toshiba Corp Nor type decoder circuit
JPS55112039A (en) * 1979-02-22 1980-08-29 Nec Corp Logic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5486242A (en) * 1977-12-21 1979-07-09 Toshiba Corp Nor type decoder circuit
JPS55112039A (en) * 1979-02-22 1980-08-29 Nec Corp Logic circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186198A (en) * 1983-04-08 1984-10-22 Seiko Epson Corp Semiconductor storage device
JPS60165119A (en) * 1984-02-08 1985-08-28 Nec Corp Multi-input cmos logic circuit
JPS63141412A (en) * 1986-12-03 1988-06-13 Toshiba Corp Logic circuit
FR2768872A1 (en) * 1997-09-25 1999-03-26 Sgs Thomson Microelectronics OR-EXCLUSIVE LOGIC HOLDER WITH FOUR ADDITIONAL TWO TO TWO AND TWO ADDITIONAL OUTPUTS, AND FREQUENCY MULTIPLIER INCORPORATING IT
EP0905907A1 (en) * 1997-09-25 1999-03-31 STMicroelectronics SA Exclusive OR gate with four two by two complementary inputs and two complementary outputs and frequency multiplier using the same
EP1277283B1 (en) * 2000-03-07 2004-09-08 Honeywell International Inc. High speed logic family

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