JPS57203332A - Lsi input circuit - Google Patents

Lsi input circuit

Info

Publication number
JPS57203332A
JPS57203332A JP56087957A JP8795781A JPS57203332A JP S57203332 A JPS57203332 A JP S57203332A JP 56087957 A JP56087957 A JP 56087957A JP 8795781 A JP8795781 A JP 8795781A JP S57203332 A JPS57203332 A JP S57203332A
Authority
JP
Japan
Prior art keywords
gate
circuit
input
output
fet4b
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56087957A
Other languages
Japanese (ja)
Inventor
Junichi Yoshida
Haruhiko Nishio
Seiichi Shibazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RIKOO TOKEI KK
Ricoh Elemex Corp
Original Assignee
RIKOO TOKEI KK
Ricoh Elemex Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RIKOO TOKEI KK, Ricoh Elemex Corp filed Critical RIKOO TOKEI KK
Priority to JP56087957A priority Critical patent/JPS57203332A/en
Publication of JPS57203332A publication Critical patent/JPS57203332A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To miniaturize an overall structure with a reduction of power consumption and at the same time to obtain a stable logical output for an LSI input circuit, by setting a 2-inpute gate connected to the gate side of an MOS type FET at the output part of an input circuit and using the output part of the 2- input gate for a circuit output part. CONSTITUTION:A protecting circuit 3 is connected to an input terminal 1 of an LSI input circuit, and an MOS type FET4b is connected to the next stage of the circuit 3. Thus a logical signal is delivered in accordance with ON or OFF of a changeover switch 2. The output side of a 2-input gate 7 is connected to the gate side of the FET4b. An all-resetting circuit 6 is connected to the input of one side of the gate 7; while the output side of the circuit 3 and the drain of the FET4b are connected to the other input. The output part of the gate 7 is used for the output of the input circuit. The ON or OFF state of the FET4b is assuredly maintained by the output of the gate 7. Thus power consumption is reduced, and at the same time a stable logical output is obtained.
JP56087957A 1981-06-08 1981-06-08 Lsi input circuit Pending JPS57203332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56087957A JPS57203332A (en) 1981-06-08 1981-06-08 Lsi input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56087957A JPS57203332A (en) 1981-06-08 1981-06-08 Lsi input circuit

Publications (1)

Publication Number Publication Date
JPS57203332A true JPS57203332A (en) 1982-12-13

Family

ID=13929343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56087957A Pending JPS57203332A (en) 1981-06-08 1981-06-08 Lsi input circuit

Country Status (1)

Country Link
JP (1) JPS57203332A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6369336U (en) * 1986-10-22 1988-05-10

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6369336U (en) * 1986-10-22 1988-05-10

Similar Documents

Publication Publication Date Title
JPS6471217A (en) Output buffer circuit
JPS5480041A (en) Decoder circuit using power switch
JPS57109089A (en) Initial value resetting circuit for operational amplifier
EP0203384A3 (en) Multiple input circuit for field effect transistors
CA2087533A1 (en) Three Terminal Non-Inverting Transistor Switch
JPS57203332A (en) Lsi input circuit
JPS5662427A (en) Logic circuit
JPS55143836A (en) Two-way switch
JPS5776925A (en) Mos type circuit
JPS5746535A (en) Mos type circuit
JPS5765927A (en) Logical operation circuit
JPS573431A (en) Complementary mos logical circuit
JPS5535574A (en) Logic device
JPS54104737A (en) Semiconductor integrated circuit device
JPS56117388A (en) Address buffer circuit
JPS57157639A (en) Semiconductor circuit
JPS57197930A (en) Logical circuit
JPS6441924A (en) Logic circuit
EP0333183A3 (en) Current switching circuit
JPS6412721A (en) Input/output circuit
JPS57157637A (en) Buffer circuit device
JPS57101406A (en) Mos analog signal amplifying circuit
JPS57121315A (en) Flip-flop circuit
JPS55136725A (en) Semiconductor logic circuit
JPS5550732A (en) Integrated latch circuit