JPS57157637A - Buffer circuit device - Google Patents

Buffer circuit device

Info

Publication number
JPS57157637A
JPS57157637A JP56043305A JP4330581A JPS57157637A JP S57157637 A JPS57157637 A JP S57157637A JP 56043305 A JP56043305 A JP 56043305A JP 4330581 A JP4330581 A JP 4330581A JP S57157637 A JPS57157637 A JP S57157637A
Authority
JP
Japan
Prior art keywords
type
input
outputs
signal
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56043305A
Other languages
Japanese (ja)
Inventor
Sadahiro Yasuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56043305A priority Critical patent/JPS57157637A/en
Publication of JPS57157637A publication Critical patent/JPS57157637A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

PURPOSE:To obtain two different combined outputs by changing an input signal into a ternary signal, by connecting in common the input of an input buffer circuit consisting of N type and P type MOSFETs. CONSTITUTION:A titled circuit is composed of a series body of an N type depletion MOSFET 8 and an N type enhancement MOSFET 9 and another series body of a P type enhancement MOSFET 10 and a P type depletion MOSFET 11. The gate of both the enhancement MOSFETs 9 and 10 is connected to each other and connected in common to an input terminal 1. Outputs 20 and 21 are issued from FETs 9 and 10, respectively. When an input signal from the external signal input terminal 1 is 1, the combined outputs (20, 21) of the input buffer are (0, -1), when the input signal is 0, said inputs are (1, -1) when the input signal is -1, said outputs are (1, 0).
JP56043305A 1981-03-25 1981-03-25 Buffer circuit device Pending JPS57157637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56043305A JPS57157637A (en) 1981-03-25 1981-03-25 Buffer circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56043305A JPS57157637A (en) 1981-03-25 1981-03-25 Buffer circuit device

Publications (1)

Publication Number Publication Date
JPS57157637A true JPS57157637A (en) 1982-09-29

Family

ID=12660074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56043305A Pending JPS57157637A (en) 1981-03-25 1981-03-25 Buffer circuit device

Country Status (1)

Country Link
JP (1) JPS57157637A (en)

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