JPS5798050A - Trouble discrimination of logic circuit device - Google Patents
Trouble discrimination of logic circuit deviceInfo
- Publication number
- JPS5798050A JPS5798050A JP55174707A JP17470780A JPS5798050A JP S5798050 A JPS5798050 A JP S5798050A JP 55174707 A JP55174707 A JP 55174707A JP 17470780 A JP17470780 A JP 17470780A JP S5798050 A JPS5798050 A JP S5798050A
- Authority
- JP
- Japan
- Prior art keywords
- trouble
- operations
- register
- output
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To detect a trouble of a logic circuit when the output information on one output terminal is constant and to discriminate easily said trouble, and applying the information of the random pattern specified times to the plural input terminal, monitoring a change in the output information from each output terminal. CONSTITUTION:To the plural input terminals P0-Pn of a trouble discrimination device, a logic circuit device (not illustrated) is connected on its plural output terminals P'0-P'n, where the result of discrimination on a trouble is output. In the register 1 of this device, the information that is input to the terminals P0- Pn is temporarily stored, the result of logical operations is stored in a register 2, in a register 3, the result of OR operation is stored, in an AND operations circuit 4, AND operations of the stored contents of registers 1, 2 are carried out, and in an OR logical operation circuit 5, OR operations are applied to the stored contents of registers 1, 3. After the termination of these operations, OR operations between inverted values of the contents of the register 2 and these of the register 3 are carried out in an OR circuit 7, and when one of the terminals P'0-P'n is constant, it is decided as a trouble. Thus, the decision on the trouble is facilitated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55174707A JPS5798050A (en) | 1980-12-12 | 1980-12-12 | Trouble discrimination of logic circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55174707A JPS5798050A (en) | 1980-12-12 | 1980-12-12 | Trouble discrimination of logic circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5798050A true JPS5798050A (en) | 1982-06-18 |
Family
ID=15983245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55174707A Pending JPS5798050A (en) | 1980-12-12 | 1980-12-12 | Trouble discrimination of logic circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5798050A (en) |
-
1980
- 1980-12-12 JP JP55174707A patent/JPS5798050A/en active Pending
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