JPS641327A - Or circuit device - Google Patents

Or circuit device

Info

Publication number
JPS641327A
JPS641327A JP62156963A JP15696387A JPS641327A JP S641327 A JPS641327 A JP S641327A JP 62156963 A JP62156963 A JP 62156963A JP 15696387 A JP15696387 A JP 15696387A JP S641327 A JPS641327 A JP S641327A
Authority
JP
Japan
Prior art keywords
level
input signal
circuit device
transistor
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62156963A
Other languages
Japanese (ja)
Other versions
JPH011327A (en
Inventor
Masafumi Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62156963A priority Critical patent/JPS641327A/en
Publication of JPH011327A publication Critical patent/JPH011327A/en
Publication of JPS641327A publication Critical patent/JPS641327A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the number of elements used in an OR circuit device, by setting a nonconductive state between two conductive terminals when a 1st input signal is low in logic level and a conductive state between the two terminals when the 1st input signal is high in logic level.
CONSTITUTION: Since the transistor P1 of an inverter circuit 1 is turned off and the other transistor N1 is turned on when the 1st input signal is high in level, an output signals C becomes low in level. Therefore, at the next-stage switching circuit 2, its output signals Y becomes high in level regardless of a 2nd input signal B. Since the transistor P1 is turned on and transistor N1 is turned off when the input signal A is low in level, the output signal C becomes high in level. As a result, the 2nd input signal B is outputted from an output terminal (y) as it is as the output signal Y. When the operation of this circuit device is expressed in a logical expression, the expression becomes Y=A+B and this circuit device functions as a two-input OR gate circuit. Therefore, the number of the elements used in this circuit device can be reduced.
COPYRIGHT: (C)1989,JPO&Japio
JP62156963A 1987-06-23 1987-06-23 Or circuit device Pending JPS641327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62156963A JPS641327A (en) 1987-06-23 1987-06-23 Or circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62156963A JPS641327A (en) 1987-06-23 1987-06-23 Or circuit device

Publications (2)

Publication Number Publication Date
JPH011327A JPH011327A (en) 1989-01-05
JPS641327A true JPS641327A (en) 1989-01-05

Family

ID=15639144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62156963A Pending JPS641327A (en) 1987-06-23 1987-06-23 Or circuit device

Country Status (1)

Country Link
JP (1) JPS641327A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166555A (en) * 1990-05-31 1992-11-24 Nec Corporation Drive circuit comprising a subsidiary drive circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166555A (en) * 1990-05-31 1992-11-24 Nec Corporation Drive circuit comprising a subsidiary drive circuit

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