JPS56127244A - Operation controller - Google Patents
Operation controllerInfo
- Publication number
- JPS56127244A JPS56127244A JP3052980A JP3052980A JPS56127244A JP S56127244 A JPS56127244 A JP S56127244A JP 3052980 A JP3052980 A JP 3052980A JP 3052980 A JP3052980 A JP 3052980A JP S56127244 A JPS56127244 A JP S56127244A
- Authority
- JP
- Japan
- Prior art keywords
- cpu101
- opened
- selectively
- chip
- taken
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To realize a high speed and simplification for the process of multiplication for an operation controller that is formed into a chip with the high-integration semiconductor, by providing a means which delivers both the hihger and lower ranks of the result of operation in different timings at the inside multiplication function part. CONSTITUTION:In the initialization mode or the reading cycle mode, the gate circuit G1 opens by the control signal supplied from a 1-chip CPU101. Then the microinstruction read out of the external control memory part 102 is taken into the CPU101. In this case, the gate circuit G4 closes to isolate the common bus 103. Furthermore either one of the gate circuits G2 and G3 is opened selectively, and either one of the TEST0 and TEST1 external signal groups is taken into the CPU101 simultaneously with the microinstruction. The circuit G4 is opened in the modes other than the lead cycle mode, and the gate circuits G5-G7 are opened selectively to be connected selectively to the bus 103. Thus the data is transferred among the CPU101, address converting mechanism 105, main memory part and other input/output devices respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3052980A JPS56127244A (en) | 1980-03-11 | 1980-03-11 | Operation controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3052980A JPS56127244A (en) | 1980-03-11 | 1980-03-11 | Operation controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56127244A true JPS56127244A (en) | 1981-10-05 |
Family
ID=12306322
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3052980A Pending JPS56127244A (en) | 1980-03-11 | 1980-03-11 | Operation controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56127244A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60157631A (en) * | 1983-12-27 | 1985-08-17 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Integrated programmable processor |
-
1980
- 1980-03-11 JP JP3052980A patent/JPS56127244A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60157631A (en) * | 1983-12-27 | 1985-08-17 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Integrated programmable processor |
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