JPS56127244A - Operation controller - Google Patents

Operation controller

Info

Publication number
JPS56127244A
JPS56127244A JP3052980A JP3052980A JPS56127244A JP S56127244 A JPS56127244 A JP S56127244A JP 3052980 A JP3052980 A JP 3052980A JP 3052980 A JP3052980 A JP 3052980A JP S56127244 A JPS56127244 A JP S56127244A
Authority
JP
Japan
Prior art keywords
cpu101
opened
selectively
chip
taken
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3052980A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Fumitaka Sato
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3052980A priority Critical patent/JPS56127244A/en
Publication of JPS56127244A publication Critical patent/JPS56127244A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22Microcontrol or microprogram arrangements
    • G06F9/26Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262Arrangements for next microinstruction selection
    • G06F9/264Microinstruction selection based on results of processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To realize a high speed and simplification for the process of multiplication for an operation controller that is formed into a chip with the high-integration semiconductor, by providing a means which delivers both the hihger and lower ranks of the result of operation in different timings at the inside multiplication function part. CONSTITUTION:In the initialization mode or the reading cycle mode, the gate circuit G1 opens by the control signal supplied from a 1-chip CPU101. Then the microinstruction read out of the external control memory part 102 is taken into the CPU101. In this case, the gate circuit G4 closes to isolate the common bus 103. Furthermore either one of the gate circuits G2 and G3 is opened selectively, and either one of the TEST0 and TEST1 external signal groups is taken into the CPU101 simultaneously with the microinstruction. The circuit G4 is opened in the modes other than the lead cycle mode, and the gate circuits G5-G7 are opened selectively to be connected selectively to the bus 103. Thus the data is transferred among the CPU101, address converting mechanism 105, main memory part and other input/output devices respectively.
JP3052980A 1980-03-11 1980-03-11 Operation controller Pending JPS56127244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3052980A JPS56127244A (en) 1980-03-11 1980-03-11 Operation controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3052980A JPS56127244A (en) 1980-03-11 1980-03-11 Operation controller

Publications (1)

Publication Number Publication Date
JPS56127244A true JPS56127244A (en) 1981-10-05

Family

ID=12306322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3052980A Pending JPS56127244A (en) 1980-03-11 1980-03-11 Operation controller

Country Status (1)

Country Link
JP (1) JPS56127244A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60157631A (en) * 1983-12-27 1985-08-17 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Integrated programmable processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60157631A (en) * 1983-12-27 1985-08-17 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Integrated programmable processor

Similar Documents

Publication Publication Date Title
JPS55129847A (en) Access system of memory unit
EP0188902A3 (en) Single-chip programmable controllers
JPS57176587A (en) Semiconductor ram device
JPS6491074A (en) Memory-contained logic lsi and testing thereof
DE3583493D1 (en) INTEGRATED SEMICONDUCTOR MEMORY.
JPS56127244A (en) Operation controller
JPS554735A (en) Semiconductor memory
JPS578858A (en) Integrated circuit package
JPS56152060A (en) Semiconductor device
JPS5537602A (en) Circuit used for simulation of integrated-circuit element
JPS6477142A (en) Semiconductor integrated circuit
JPS54144830A (en) Data memory unit
JPS5798172A (en) Memory access controlling circuit
JPS5746386A (en) Semiconductor storage device
JPS5525109A (en) Logic circuit
JPS6435639A (en) Rom/ram memory access switching circuit
JPS5720979A (en) Memory control system
JPS6439699A (en) Semiconductor memory device
JPS55134443A (en) Data processing unit
JPS6443891A (en) Semiconductor memory device
JPS57106229A (en) Cmos multiinput storage circuit
JPS5718085A (en) Rom
JPS6431257A (en) Semiconductor integrated circuit
JPS5447538A (en) Channel device
JPS54123841A (en) Semiconductor integrated memory element