JPS5746386A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS5746386A
JPS5746386A JP12189580A JP12189580A JPS5746386A JP S5746386 A JPS5746386 A JP S5746386A JP 12189580 A JP12189580 A JP 12189580A JP 12189580 A JP12189580 A JP 12189580A JP S5746386 A JPS5746386 A JP S5746386A
Authority
JP
Japan
Prior art keywords
data
output signal
input
ports
address line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12189580A
Other languages
Japanese (ja)
Inventor
Hiromichi Miyakoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12189580A priority Critical patent/JPS5746386A/en
Publication of JPS5746386A publication Critical patent/JPS5746386A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To reduce the input/output process that is performed by a program, by selecting a specified address line of a RAM, then carrying out the writing control of a data. CONSTITUTION:The data are applied to input ports 121-124, and at the same time an address line 323 is selected. Under such conditions, the data write control signal W is supplied to an AND gate circuit 33. Thus the output signal of the circuit 33 is set at a high level. When this high-level output signal is applied to each control input terminal, tri-state buffer circuits 341-344 open respectively. Then the data applied to the ports 121-124 are transmitted to data lines 311-314 respectively and furthermore to an inner bus line 5. Thus the reading of data is carried out.
JP12189580A 1980-09-03 1980-09-03 Semiconductor storage device Pending JPS5746386A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12189580A JPS5746386A (en) 1980-09-03 1980-09-03 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12189580A JPS5746386A (en) 1980-09-03 1980-09-03 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS5746386A true JPS5746386A (en) 1982-03-16

Family

ID=14822556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12189580A Pending JPS5746386A (en) 1980-09-03 1980-09-03 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS5746386A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03226594A (en) * 1990-01-30 1991-10-07 Riken Light Metal Ind Co Ltd Formation of spotted pattern on aluminum or aluminum alloy by coating and coating material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03226594A (en) * 1990-01-30 1991-10-07 Riken Light Metal Ind Co Ltd Formation of spotted pattern on aluminum or aluminum alloy by coating and coating material

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